Embodiments of the invention are directed to a method and resulting structures for forming optically readable chip identification (CID) codes using dummy controlled collapse chip connection (C4) bumps. In a non-limiting embodiment of the invention, a product chip is formed on a wafer. A chip location identifier including a plurality of controlled collapse chip connection (C4) bumps is formed on a surface of the product chip. The chip location identifier encodes a unique location of the product chip on the wafer prior to dicing. The plurality of C4 bumps are arranged into one or more optically readable alphanumeric characters.

A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.

A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface, a first through via plug passing through the core substrate, a pad disposed on the bump-side surface, in contact with the first through via plug, and a first thickness enhancing conductive pattern disposed on a surface of the pad, which is away from the bump-side surface.

The invention provides a circuit substrate and a semiconductor package structure. The circuit substrate includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface. A first through via plug passes through the core substrate. A first conductive line pattern and a second conductive line pattern adjacent to the first conductive line are disposed on the chip-side surface. A pad is disposed on the bump-side surface. The first through via plug is in direct contact with and partially overlapping the first conductive line pattern and the pad. The first conductive line pattern, the second conductive line pattern and the first through via plug are configured to transmit voltage supplies of the same type.

An integrated circuit includes a semiconductor chip, a first bump row, and a second bump row. The semiconductor chip has a first edge oriented in a first planar direction. The first bump row includes a plurality of first bumps aligned in the first planar direction along the first edge, and the second bump row includes a plurality of second bumps aligned in the first planar direction. The second bump row is located farther from the first edge of the semiconductor chip than the first bump row. A first width of the first bumps in the first planar direction is narrower than a second width of the second bumps in the first planar direction.

Packages with wafer level land grid arrays are described. In an embodiment, a package includes a die and a package routing layer over the die, where the package routing layer includes a first land that spans over a first set of vias, and a second land that spans over a second set of vias, where the vias may be connected to a metal redistribution line or directly connected to die contact pad of the die.

In a flip chip package, lines, an identification line and a dummy line are provided on a first surface of a light-transmissive carrier, and a supportive layer is disposed on a second surface of the light-transmissive carrier. Bumps and an identification bump of a chip are bonded to the lines and the identification line, respectively. Shadows of the dummy line, the identification line and the identification bump which are projected on the second surface are visible from an opening of the supportive layer. The shadows can be inspected through the opening so as to know whether the bumps are bonded to the lines correctly.