A semiconductor device is vertically mounted on a medium such as a printed circuit board (PCB). The semiconductor device comprises a block of semiconductor dies, mounted in a vertical stack without offset. Once formed and encapsulated, side grooves may be formed in the device exposing electrical conductors of each die within the device. The electrical conductors exposed in the grooves mount to electrical contacts on the medium to electrically couple the semiconductor device to the medium.

A die stack that includes a first chip die, a second chip die connected to the first chip die by one or more controlled collapse chip connection (“C4”) solder bump bonds, and a spacer die interposed between the first and second chip dies. The spacer die includes through holes for the one or more C4 solder bumps, and has a thickness such that when the first and second chip dies are compressed into contact with the spacer die, the spacer die thickness is a minimum defined spacing between the first and second chip dies, and the spacer die operates as a hard stop against compression of the die stack after the first and second chip dies are compressed into contact with the spacer die.

Provided is a semiconductor package including a first chip substrate including a first surface and a second surface, a through via passing through the first chip substrate, an upper passivation layer including a trench on the second surface of the first chip substrate, the trench exposing at least a portion of the second surface of the first chip substrate, an upper pad electrically connected with the through via on the trench, a second chip substrate including a third surface and a fourth surface, a lower pad electrically connected to the second chip substrate on the third surface of the second chip substrate, and a connection bump electrically connecting the upper pad with the lower pad and contacting the lower pad, wherein a width of the connection bump increases as the connection bump becomes farther away from the first surface of the first chip substrate.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and a first chip connection structure disposed between the first semiconductor chip and the second semiconductor chip. The first chip connection structure includes a first insertion connection structure connected to the first semiconductor chip, a first recess connection structure connected to the second semiconductor chip, and a first contact layer interposed between the first insertion connection structure and the first recess connection structure. The first recess connection structure includes a base and a side wall which defines a recess. A portion of the first insertion connection structure is disposed in the recess. A portion of the first contact layer is disposed in the recess, and the first contact layer covers at least a portion of a bottom surface of the side wall.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.

A semiconductor package includes a package substrate and a plurality of sub-packages provided on the package substrate. Each of the plurality of sub-packages includes a semiconductor chip, an interposer provided adjacent to the semiconductor chip, the interposer including a plurality of first through-silicon vias, an encapsulator provided between the semiconductor chip and the interposer, and a redistribution layer provided on the interposer, the encapsulator and the semiconductor chip. The semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite the first surface and a plurality of chip pads provided on the first surface. The redistribution layer includes a plurality of redistribution pads and a horizontal wiring provided between the plurality of redistribution pads and the plurality of first through-silicon vias. The redistribution layer is provided on the second surface of the semiconductor substrate, and extends on the encapsulator and the interposer.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

A semiconductor device and a semiconductor package including the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has a larger cross-section surface area than the second bump.

Systems, apparatuses, and methods related to dynamic random access memory (DRAM), such as finer grain DRAM, are described. For example, an array of memory cells in a memory device may be partitioned into regions. Each region may include a plurality of banks of memory cells. Each region may be associated with a data channel configured to communicate with a host device. In some examples, each channel of the array may include two or more data pins. The ratio of data pins per channel may be two or four in various examples. Other examples may include eight data pins per channel.