A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.

This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad electrically connected to the first semiconductor layer; a second pad comprising multiple sidewalls electrically connected to the second semiconductor layer; and a metal layer formed on the semiconductor stack, wherein the metal layer surrounds the multiple sidewalls of the second pad and the metal layer is separated from the second pad.

Shielded extremely high frequency (EHF) connector assemblies are disclosed herein. In some embodiments, a first extremely high frequency (EHF) shielded connector assembly configured to be coupled with a second EHF shielded connector assembly. The first EHF connector assembly can include a first EHF communication unit operative to contactlessly communicate EHF signals with a second EHF communication unit included in the second EHF shielded connector assembly. The first connector can include a connector interface that includes a configuration to interface with a respective connector interface of the second EHF shield connector assembly, and several different material compositions that, in conjunction with the configuration, provide shielding to prevent or substantially reduce EHF signal leakage when the first EHF assembly connector is coupled to the second EHF assembly connector and the first EHF communication unit is contactlessly communicating EHF signals with the second EHF communication unit.

Disclosed herein is a light emitting device package and a light emitting device package module. The light emitting device package includes: a base including a cavity; a first light emitting device disposed in the cavity, the first light emitting device including a first light emitting element configured to produce light having a first peak wavelength and a first fluorescent layer covering a top and side surfaces of the first light emitting element; and a second light emitting device disposed in the cavity, the second light emitting device including a second light emitting element configured to produce light having a second peak wavelength and a second fluorescent layer covering a top and side surfaces of the second light emitting element, wherein the first fluorescent layer is configured to convert the light having the first peak wavelength of the first light emitting element to light having a third peak wavelength, and the second fluorescent layer is configured to convert the light having the second peak wavelength of the second light emitting element to light having a fourth peak wavelength.

A semiconductor device has a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area. An underfill material is deposited between the semiconductor die and substrate. The semiconductor die includes a flexible property. The vertical interconnect structure includes a flexible property. The substrate includes a flexible property.

A passive tunable integrated circuit (PTIC) includes a semiconductor die (die) having a plurality of barium strontium titanate (BST) tunable capacitors. The plurality of BST tunable capacitors collectively define a capacitative area of the die. At least one electrical contact is electrically coupled with the plurality of BST tunable capacitors. A redistribution layer electrically couples the at least one electrical contact with at least one electrically conductive contact pad (contact pad). The at least one contact pad is located over the capacitative area. A bump electrically couples with the at least one contact pad and is located over the capacitative area. An electrically insulative layer couples between each contact pad of the PTIC and the plurality of BST tunable capacitors.

RFID inlays or straps may be assembled using impulse heating of metal precursors. Metal precursors are applied to and/or included in contacts on an RFID IC and/or terminals on a substrate. During assembly of the tag, the IC is disposed onto the substrate such that the IC contacts physically contact either the substrate terminals or metal precursors that in turn physically contact the substrate terminals. Impulse heating is then used to rapidly apply heat to the metal precursors, processing them into metallic structures that electrically couple the IC contacts to the substrate terminals.

A semiconductor device substrate and wiring member including a first noble metal plating layer to become internal terminals is formed at predetermined sites on a metal plate, a metal plating layer is formed on the first noble metal plating layer as having a same shape as the first noble metal plating layer, a second noble metal plating layer to become external terminals is formed on a part of the metal plating layer, and a height of a surface of the second noble metal plating layer from a surface of the metal plate is larger than a height of a surface of the first noble metal plating layer from the surface of the metal plate.