Described herein is a method of forming wafer-level packages from a wafer. The method includes adhesively attaching front sides of first integrated circuits within the wafer to back sides of second integrated circuits such that pads on the front sides of the first integrated circuits and pads on front sides of the second integrated circuits are exposed. The method further includes forming a laser direct structuring (LDS) activatable layer over the front sides of the first integrated circuits and the second integrated circuits and over edges of the second integrated circuits, and forming desired patterns of structured areas within the LDS activatable layer. The method additionally includes metallizing the desired patterns of structured areas to form conductive areas within the LDS activatable layer.

A display device may include: a first power line and a second power line located on a substrate; a first electrode electrically connected to the first power line through a first contact portion; a second electrode electrically connected to the second power line through a second contact portion and spaced apart from the first electrode in a first direction; a light emitting element located on the first electrode and the second electrode; and a pixel circuit including a transistor and a storage capacitor, and electrically connected to the light emitting element. The first contact portion may include a plurality of first contact portions successively arranged in the first direction. In a plan view, the storage capacitor may have a shape extending in a second direction different from the first direction.

A display device includes a first pattern and a second pattern, which are spaced apart from each other in an emission area. A light emitting element is disposed between the first pattern and the second pattern. A first electrode is disposed on the first pattern. A second electrode is disposed on the second pattern. A light blocking pattern is disposed under the light emitting element and between the first pattern and the second pattern.

A microelectronic assembly is disclosed, comprising: a substrate having a core made of glass; and a first integrated circuit (IC) die and a second IC die coupled to a first side of the substrate. The core comprises a cavity, a third IC die is located within the cavity, and the core further comprises one or more conductive through-glass via (TGV) that facilitates electrical coupling between the first side of the substrate and an opposing second side of the substrate. In some embodiments, the cavity is a blind cavity; in other embodiments, the cavity is a through-hole. In some embodiments, the third IC die merely provides lateral coupling between the first IC die and the second IC die; in other embodiments, the third IC die also provides electrical coupling between the first side and the second side of the substrate with through-silicon vias.

A method of making a micro-module structure comprises providing a substrate, the substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post, the component having a component top side and a component bottom side opposite the component top side, the component bottom side disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

A method of forming a semiconductor package device includes: providing a substrate; bonding a first die to an upper surface of the substrate through a bonding layer; bonding a second die to the upper surface of the substrate through the bonding layer, the second die laterally separated from the first die; depositing an insulation material between the first die and the second die and filling a gap measured between sidewalk of the first die and the second die; forming a first interconnect layer over the first die and the second die to form the semiconductor package device; and performing a testing operation on semiconductor package device with the substrate in place. A Young's modulus of the substrate is greater than that of the insulation material.

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.

A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 40 nm alignment error; and a via disposed through the first level, where the first level thickness is less than two microns.

A display panel manufacturing apparatus and a display panel manufacturing method are provided. A display panel manufacturing apparatus manufactures a display panel which is on a lower stage and includes light emitting elements. The display panel manufacturing apparatus includes: a power supply for supplying an alignment voltage for aligning the light emitting elements on the display panel; and an upper stage including a probe unit to provide the alignment voltage to the display panel and magnetic sensors to sense an alignment state of the light emitting elements.