The present invention is a method for producing an electronic device having a drive circuit including a solar cell structure, the method including the steps of: obtaining a bonded wafer by bonding a first wafer having a plurality of independent solar cell structures including a compound semiconductor, the solar cell structures being formed on a starting substrate by epitaxial growth, and a second wafer having a plurality of independent drive circuits formed, so that the plurality of solar cell structures and the plurality of drive circuits are respectively superimposed; wiring the bonded wafer so that electric power can be supplied from the plurality of solar cell structures to the plurality of drive circuits respectively; and producing an electronic device having the drive circuit including the solar cell structure by dicing the bonded wafer. This provides a method for producing an electronic device including a drive circuit and a solar cell structure in one chip and having a suppressed production cost.

The present invention provides a semiconductor package structure including a first stacked structure and a second stacked structure, which is stacked on the first stacked structure. The first stacked structure includes a first dielectric layer, a first power chip, a first conductive connecting element, a first conductive pillar and a first patterned conductive layer. The second stacked structure includes a second dielectric layer, a second power chip, a second conductive connecting element, a second conductive pillar, a second patterned conductive layer, and a third patterned conductive layer. The first power chip and the second power chip are stacked to provide a smaller volume semiconductor package structure, that the first power chip and the second power chip may be directly electrically connected through the circuit structure and may eliminate the related disadvantages of the lead frame. In addition, a manufacturing method of a semiconductor package structure is also disclosed.

A micro-light-emitting diode mounting board includes a substrate having a mount surface receiving multiple micro-LEDs, and at least one pixel unit located on the mount surface and including the multiple micro-LEDs having different emission colors to operate as a basic element of display. The multiple micro-LEDs include vertical stacks of multiple first electrodes, multiple emissive layers, and multiple second electrodes. The at least one pixel unit includes a power electrode pad connected to each of the multiple second electrodes. The power electrode pad is spaced from each of the multiple first electrodes by a distance greater than an interelectrode distance between adjacent first electrodes of the multiple first electrodes.

A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.

A semiconductor device, the device including: a first substrate; a first metal layer disposed over the substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 100 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where a typical thickness of the fourth metal layer is at least 50% greater than a typical thickness of the third metal.

A semiconductor device includes a first semiconductor body including a substrate having a first thickness, wherein the first semiconductor body includes a first active zone that generates or receives radiation, and a second semiconductor body having a second thickness smaller than the first thickness and including a tear-off point is arranged on the substrate and connected in an electrically conducting manner to the first semiconductor body, wherein the second semiconductor body includes a second active zone that generates or receives radiation, and the second active zone generates radiation and the first active zone detects the radiation, and the first semiconductor body includes contacts on its underside for connection to the semiconductor device.

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.

An electronic circuit device according to the present invention includes a base substrate having a wiring layer, at least one first electronic circuit element having a first surface fixed to the base substrate and having a connection part on a second surface opposed to the first surface, a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing the first electronic circuit element on the base substrate and embedding a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the first electronic circuit element, the second wiring photo via arranged at the outer periphery of the first electronic circuit element and electrically connected to a connection part of the wiring layer, the wiring arranged on the second surface and electrically connected to the first wiring photo via and the second wiring photo via.

A display device includes a first electrode and a second electrode disposed on a substrate, the first and second electrodes being spaced apart from each other with a spaced area disposed between the first and second electrodes, an insulating layer disposed on the first electrode and the second electrode, the insulating layer filling the spaced area, and a light emitting element disposed on the insulating layer and having a first end disposed on the first electrode and a second end opposite to the first end. The insulating layer includes a first opening adjacent to the first end and exposing the insulating layer, and the spaced area is adjacent to the second end of the light emitting element.

A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.