The present disclosure relates to an LED display device, and more particularly, to an LED display device including a repair structure for a deteriorated pixel. In the present disclosure, a sub LED electrically coupled to first and second connecting electrodes for applying a voltage to a LED is disposed on a deteriorated LED. Thus, deterioration of a display quality due to a deteriorated pixel is prevented. Since it is not required to remove a deteriorated LED, a fabrication cost is reduced and a process efficiency is improved.

A method includes bonding a first wafer to a second wafer, and performing a trimming process on the first wafer. An edge portion of the first wafer is removed. After the trimming process, the first wafer has a first sidewall laterally recessed from a second sidewall of the second wafer. A protection layer is deposited and contacting a sidewall of the first wafer, which deposition process includes depositing a non-oxygen-containing material in contact with the first sidewall. The method further includes removing a horizontal portion of the protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.

A display device includes: a substrate having an emission area and a non-emission area; a first bank in the non-emission area of the substrate and having an opening; electrodes on the first bank and spaced apart from each other; a second bank on the electrodes; and light emitting elements on the second bank between the electrodes. The second bank has a first area overlapping the light emitting elements and a second area in the opening in the first bank.

A display device includes a plurality of bank patterns disposed on a substrate and spaced apart from each other, a plurality of electrodes disposed on the substrate and extended parallel to each other and spaced apart from each other, an insulating layer disposed on the plurality of electrodes and the plurality of bank patterns, and a plurality of light emitting elements disposed on the insulating layer, having both ends disposed on the plurality of electrodes, wherein the plurality of bank patterns include sides facing each other, and portions of the plurality of light emitting elements are disposed on the sides of the plurality of bank patterns.

A preparation method of a thin power device comprising the steps of steps S1, S2 and S3. In step S1, a substrate is provided. The substrate comprises a first set of first contact pads and a second set of second contact pads arranged at a front surface and a back surface of the substrate respectively. Each first contact pad of the first set of contact pads is electrically connected with a respective second contact pad of the second set of contact pads via a respective interconnecting structure formed inside the substrate. A through opening is formed in the substrate aligning with a third contact pad attached to the back surface of the substrate. The third contact pad is not electrically connected with the first set of contact pads. In step S2, a semiconductor chip is embedded into the through opening. A back metal layer at a back surface of the semiconductor chip is attached to the third contact pad. In step S3, a respective electrode of a plurality of electrodes at a front surface of the semiconductor chip is electrically connected with said each first contact pad of the first set of contact pads via a respective conductive structure of a plurality of conductive structures.

The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 μm to about 0.2 μm.

A semiconductor package includes at least one first semiconductor device, a first molding compound, a dielectric layer, at least one conductive feature and at least one compensating structure. The first molding compound is present on at least one sidewall of the first semiconductor device. The dielectric layer is present on the first molding compound and the first semiconductor device. The conductive feature present is at least partially in the dielectric layer and electrically connected to the first semiconductor device. The compensating structure is present at least partially in the dielectric layer. The compensating structure is monolithically connected to the first molding compound.

A display device includes a first display substrate including a light emitting element layer, a second display substrate facing the first display substrate and including a light blocking member and a color conversion layer, a coupling member that connects the first display substrate and the second display substrate to each other, and a filling member disposed between the first display substrate and the second display substrate. The filling member includes a photoinitiator that initiates by absorbing light of a wavelength band in a range of about 380 nm to about 500 nm, and the light blocking member and the color conversion layer cover a side of an entire surface of the second display substrate.