A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Discussed is a display device including: a substrate; a power wiring and a ground wiring disposed on the substrate and spaced apart from each other; a driving thin film transistor (TFT) disposed on the substrate and having a source terminal electrically connected to the ground wiring; at least one insulating. layer disposed on the substrate; and a pair of assembly electrodes spaced apart from each other between the at least one insulating layer and the substrate, wherein the pair of assembly electrodes is configured to generate an electric field as a voltage is applied to any one of the pair of assembly electrodes.

A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion.

The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

A packaged semiconductor device includes a substrate with first and second opposing major surfaces. A stacked semiconductor device structure is connected to the first major surface and includes a plurality of semiconductor die having terminals. Conductive interconnect structures electrically connect the terminals of the semiconductor dies together. The semiconductor dies are stacked together so that the terminals are exposed, and the stacked semiconductor device structure comprises a stepped profile. The conductive interconnect structures comprise a conformal layer that substantially follows the stepped profile.

The present disclosure provides a three-dimensional chip packaging structure and a method of making thereof. The structure includes: a plurality of chips stacked to form a staggered structure, each chip has one end hanging out from a lower chip and another end exposed out and connecting to a pad disposed on the chip, metal connecting pillars formed on the pads, a packaging layer disposed on the metal connecting pillars and the chips, a rewiring layer formed on the packaging layer, and a metal bump formed on the rewiring layer. The structure and method making it do not involve the Through-Silicon-Via (TSV) process, which is commonly used to achieve three-dimensional stacking of chips but is costly at the same time. Instead, the structure and method adopt pads and metal connecting pillars for electric connection. Also, the packaging structure does not necessitate a substrate for support, which reduces the package size.

The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer.

The present disclosure provides a chip packaging structure and method, using a back-to-back packaging structure, and realizing electrical connection between chips through TSV holes or cooperation between TSV and TMV holes, completely penetrating two chips. Thus, the TSV hole passing through a silicon material may not need to be formed in advance on the chips before bonding the chips, thereby the requirement of alignment accuracy of the chips can be reduced, and the process difficulty can be reduced. In addition, as the back-to-back packaging process is adopted, the heat dissipation efficiency of the chips can be improved, and the problem of circuit breakage due to materials with different expansion coefficients present between the chips can be avoided.

In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.