A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.

A semiconductor package includes a first sub-package on an interconnection layer. A second sub-package and a third sub-package are sequentially stacked on the first sub-package. Each of the first to third sub-packages includes a semiconductor chip and an interposing bridge. The interposing bridge includes a first through via and a second through via. The second sub-package further includes a first redistributed line electrically connecting the semiconductor chip of the second sub-package to the first through via. The third sub-package further includes a second redistributed line electrically connecting the semiconductor chip of the third sub-package to the second through via.

A semiconductor package includes an insulating layer including a first face and a second face opposite each other, a redistribution pattern including a wiring region and a via region in the insulating layer, the wiring region being on the via region, and a first semiconductor chip connected to the redistribution pattern. The first semiconductor chip may be on the redistribution pattern. An upper face of the wiring region may be coplanar with the first face of the insulating layer.

The present technology relates to a semiconductor device and a method of manufacturing the same capable of improving reliability of a glass substrate on which a wiring layer is formed. A semiconductor device is provided with a glass substrate on a front surface or front and back surfaces of which a wiring layer including one or more layers of wiring is formed, an electronic component arranged inside a glass opening formed on the glass substrate, and a redistribution layer that connects the wiring of the glass substrate and the electronic component. The present technology is applicable to, for example, a high-frequency front-end module and the like.

A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.

A power device embedded PCB includes a printed circuit board having a first major surface separated by a thickness and opposite a second major surface and an embedded power device. The embedded power device may include a power semiconductor device, an electrically and thermally conductive substrate bonded to the power semiconductor device along a first surface of the electrically and thermally conductive substrate and bonded to an electrical insulation layer on a second surface of the electrically and thermally conductive substrate opposite the first surface and a thermally conductive substrate bonded to the electrical insulation layer on a surface opposite the bonded electrically and thermally conductive substrate. The power semiconductor device, the electrically and thermally conductive substrate, the electrical insulation layer, and the thermally conductive substrate are disposed within the printed circuit board. The thermally conductive substrate forms a bondable surface adjacent the second major surface of the printed circuit board.

A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.

A semiconductor package includes a semiconductor die including a sensing component, an encapsulant laterally covering the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant, a patterned dielectric layer disposed on the top surfaces of the encapsulant and the semiconductor die, a conductive pattern disposed on and inserted into the patterned dielectric layer to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV. The top surface of the encapsulant is above and rougher than a top surface of the semiconductor die, and the sensing component is accessibly exposed by the patterned dielectric layer.

A power device embedded PCB includes a printed circuit board having a first major surface separated by a thickness and opposite a second major surface and an embedded power device. The embedded power device may include a power semiconductor device, an electrically and thermally conductive substrate bonded to the power semiconductor device along a first surface of the electrically and thermally conductive substrate and bonded to an electrical insulation layer on a second surface of the electrically and thermally conductive substrate opposite the first surface and a thermally conductive substrate bonded to the electrical insulation layer on a surface opposite the bonded electrically and thermally conductive substrate. The power semiconductor device, the electrically and thermally conductive substrate, the electrical insulation layer, and the thermally conductive substrate are disposed within the printed circuit board. The thermally conductive substrate forms a bondable surface adjacent the second major surface of the printed circuit board.