Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

An antenna substrate includes: a first substrate including an antenna pattern disposed on an upper surface of the first substrate; a second substrate having a first planar surface, an area of which is smaller than an area of a planar surface of the first substrate; and a flexible substrate connecting the first and second substrates to each other and bent to allow the first planar surface of the second substrate to face a side surface of the first substrate, which is perpendicular to the upper surface of the first substrate.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first package and a second package. The first package includes a first substrate, an electronic component, a trace layer, and a first conductive structure. The first substrate has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the first substrate. The trace layer has an uppermost conductive layer embedded in the first substrate and exposed from the first surface of the first substrate. The first conductive structure electrically connects the trace layer to the second surface of the first substrate. The second package is disposed on the first surface of the first substrate of the first package.

A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

A semiconductor package includes an outer redistributed line (RDL) structure, a first semiconductor chip disposed on the outer RDL structure, a stack module stacked on the first semiconductor chip, and a bridge die stacked on the outer RDL structure. A portion of the stack module laterally protrudes from a side surface of the first semiconductor chip. The bridge die supports the protruding portion of the stack module. The stack module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor die disposed on the inner RDL structure, and an inner encapsulant. The capacitor die acts as a decoupling capacitor of the second semiconductor chip.

The present disclosure provides a power module and a method for manufacturing the power module. The power module includes a chip, a passive element and connection pins. The connection pins are provided on a pin-out surface of the power module, and are electrically connected to at least one of a chip terminal of the chip and the passive element; a projection of the chip on the pin-out surface of the power module does not overlap with a projection of the passive element on the pin-out surface of the power module, and an angle between the terminal-out surface of the chip and the pin-out surface of the power module is greater than 45° and less than 135°.

A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to V.sub.SS and forms a ground plane. A second portion of the first conductive layer is electrically connected to V.sub.DD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

An antenna apparatus includes a ground pattern having a through-hole; an antenna pattern disposed above the ground pattern and configured to either one or both of transmit and receive a radio-frequency (RF) signal; a feed via penetrating through the through-hole and having one end electrically connected to the antenna pattern; and a meta member comprising a plurality of cells repeatedly arranged and spaced apart from each other, each of the plurality of cells comprising a plurality of conductive patterns, and at least one conductive via electrically connecting the plurality of conductive patterns to each other, wherein the meta member is disposed along at least portions of side boundaries of the antenna pattern above the ground pattern, and extends above the antenna pattern.

To reduce the wiring inductance when establishing electrical connection between a semiconductor laser and a laser driver in a semiconductor laser driving apparatus. A semiconductor laser driving apparatus includes a substrate, a laser driver, and a semiconductor laser. The substrate incorporates the laser driver. The semiconductor laser is mounted on one surface of the substrate. Connection wiring electrically connects the laser driver and the semiconductor laser to each other with a wiring inductance of 0.5 nanohenries or less. A shield suppresses flow of electromagnetic waves to/from an outside of the semiconductor laser driving apparatus for at least one of the semiconductor laser and the laser driver.

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.