A semiconductor device comprises: one or more semiconductor dice arranged on a substrate such as a leadframe, an insulating encapsulation of, e.g., LDS material molded onto the semiconductor die or dice arranged on the substrate, the encapsulation having a surface opposite the substrate, and electrically conductive formations (e.g., die-to-lead 181, 182, 183 or die-to-die 201, 202) provided in the encapsulation and coupled to the semiconductor die or dice arranged on the substrate. A tape is laminated onto the surface of the encapsulation opposite the substrate and electrically conductive contacts to the electrically conductive formations extend through the tape laminated onto the encapsulation. The length of the electrically conductive contacts is thus reduced to the thickness of the tape laminated onto the encapsulation, thus facilitating producing, e.g., “vertical” MOSFET power devices having a reduced drain-source “on” resistance, RDS.sub.ON.

A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.

The present disclosure is directed to embodiments of semiconductor device packages including a plurality of conductive vias and traces formed by an laser-direct structuring process, which includes at least a lasering step and a plating step. First ones of the plurality of conductive vias extend into an encapsulant to contact pads of a die encased within the encapsulant, and second ones of the plurality of conductive vias extend in the encapsulant to end portions of leads in the encapsulant. The second ones of the plurality of conductive vias may couple the leads to contact pads of the die. In some embodiments, the leads of the semiconductor device packages may extend outward and away from encapsulant. In some other alternative embodiments, the leads of the semiconductor device packages may extend outward and away from the encapsulant and then bend back toward the encapsulant such that an end of the lead overlaps a surface of the encapsulant at which the plurality of conductive vias are present.

A semiconductor die is arranged on a substrate and an encapsulation of laser direct structuring (LDS) material is molded onto the semiconductor die. A through mold via (TMV) extends through the encapsulation. This TMV includes a collar section that extends through a first portion of the encapsulation from an outer surface to an intermediate level of the encapsulation, and a frusto-conical section that extends from a bottom of the collar section through a second portion of the encapsulation. The collar section has a first cross-sectional area at the intermediate level. The first end of the frusto-conical section has a second cross-section area at the intermediate level. The second cross-sectional area is smaller than the first cross-sectional area. The TMV can have an aspect ratio which is not limited to 1:1.

A method for producing a semiconductor package includes providing a lead frame and a bond pad with a space therebetween. The frame is provided with a die bonded thereon and a die pad. The die, the pad, a part of the frame, a part of the bond pad and the space between the frame and the bond pad are encapsulated. Part of the first encapsulation is removed to create a cavity having a bottom surface including an exposed surface of the die, an exposed surface of the pad, an exposed surface of the bond pad and a connecting region between the exposed surface of the pad and the bond pad. The cavity is partly filled with an electrically conductive paste. The electrically conductive paste is cured to obtain an interconnect between the die pad and the bond pad. The interconnect is encapsulated.

A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.

A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.

Methods for repacking copper wire bonded microelectronic die (that is, die having bond pads bonded to copper wire bonds) are provided. In one embodiment, the repackaging method includes the step or process of obtaining a microelectronic package containing copper wire bonds and a microelectronic die, which includes bond pads to which the copper wire bonds are bonded. The microelectronic die is extracted from the microelectronic package in a manner separating the copper wire bonds from the bond pads. The microelectronic die is then attached or mounted to a Failure Analysis (FA) package having electrical contact points thereon. Electrical connections are then formed between the bond pads of the microelectronic die and the electrical contact points of the FA package at least in part by printing an electrically-conductive material onto the bond pads.

A semiconductor package includes a chip level unit including a semiconductor chip; a medium level unit; and a solder ball unit. The solder ball unit is to be connected to a circuit substrate. The medium level unit includes: a wiring pad layer on a first protection layer; a second protection layer including a pad-exposing hole on the first protection layer, a post layer in the pad-exposing hole on the wiring pad layer; and a third protection layer including a post-exposing hole on the second protection layer. A width or diameter of the post-exposing hole is smaller than a width or diameter of the pad-exposing hole; and a barrier layer is disposed in the post-exposing hole on the post layer. The solder ball unit includes a solder ball on the barrier layer.

A method produces a plurality of optoelectronic modules, and includes: A) providing a metallic carrier assembly with a plurality of carrier units; B) applying a logic chip, each having at least one integrated circuit, to the carrier units; C) applying emitter regions that generate radiation, which can be individually electrically controlled; D) covering the emitter regions and the logic chips with a protective material; E) overmolding the emitter regions and the logic chips so that a cast body is formed, which joins the carrier units, the logic chips and the emitter regions to one another; F) removing the protective material and applying electrical conductor paths to the upper sides of the logic chips and to a cast body upper side; and G) dividing the carrier assembly into the modules.