A power module is designed with balanced current flow for each power switch in parallel so that every power switch has a similar current path length. The power module can include a first plurality of power switches electrically coupled to a first region and a second plurality of power switches electrically coupled to a second region. A first plurality of conductive clips are configured to conduct a first plurality of currents and a second plurality of conductive clips are configured to conduct a second plurality of currents. The power module can include a first lead frame configured to apply positive voltage to the first region, a second lead frame configured to conduct current from the second region and a third lead frame configured to conduct current from the third region.

A semiconductor device includes: first and second semiconductor chips provided separately from each other, each semiconductor chip including a first main electrode on a top surface side and a second main electrode on a bottom surface side; and a printed circuit board provided at a circumference of the first and second semiconductor chips, the printed circuit board including a plurality of wiring layers including a first wiring layer which is an uppermost layer electrically connected to the first main electrode of the first semiconductor chip through a connection member, and a second wiring layer which is a lowermost layer electrically connected to the first wiring layer through a via and further to the second main electrode of the second semiconductor chip, and an insulating layer provided between the respective wiring layers.

In a semiconductor device, a multilayer substrate includes an insulating substrate, a first circuit board having a first semiconductor chip disposed thereon, and a second circuit board having a second semiconductor chip disposed thereon. On the multilayer substrate of the semiconductor device, a plate portion of a resin plate including a first positioning portion that regulates the position of each semiconductor chip is sandwiched between a first jumper terminal, which includes a first terminal connected to the first semiconductor chip and a first plate member perpendicular to the first terminal, and a second jumper terminal, which includes a second terminal connected to the second semiconductor chip and a second plate member perpendicular to the second terminal.

A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips provided on the conductive substrate; a printed wiring board including a first conductive layer provided on the conductive substrate, an insulating layer provided on the first conductive layer, and a second conductive layer provided on the insulating layer and electrically connected to respective first electrodes of the semiconductor chips; and a first external terminal provided on the second conductive layer to extend upward from the second conductive layer.

Provided is a semiconductor package including a heat radiation structure, a cooling system applying the semiconductor package, a substrate including a heat radiation structure, and a method of manufacturing the substrate, and more particularly, a semiconductor package including a heat radiation structure, a cooling system applying the semiconductor package, a substrate including a heat radiation structure, and a method of manufacturing the substrate, in which an area contacting a coolant enlarges through heat radiating posts having various forms and structures and a coolant flow path is formed by post holes so that heat generated from semiconductor chips may be efficiently cooled.

The semiconductor device includes a semiconductor element, a substrate supporting the semiconductor element, a sealing resin covering the semiconductor element and a part of the substrate, and a heat dissipation member. The substrate includes an obverse surface facing a first side in a thickness direction, and a reverse surface facing a second side in the thickness direction and exposed from the sealing resin. The semiconductor element is mounted on the obverse surface. The heat dissipation member is disposed on the substrate on the second side in the thickness direction. The heat dissipation member includes first bases located on the first side in the thickness direction, and first upright portions extending from the first bases to the second side in the thickness direction. The substrate includes first recesses recessed from the reverse surface to the first side in the thickness direction. The first bases are housed in the first recesses.

A first terminal is provided on a first surface of the first semiconductor package and electrically connected to a first pole side of the first semiconductor chip. A first output terminal is provided on a second surface of the first semiconductor package and electrically connected to a second pole side of the first semiconductor chip. A second output terminal is provided on a third surface of the second semiconductor package and electrically connected to the first pole side of the second semiconductor chip. A second terminal is provided on the third surface of the second semiconductor package and electrically connected to the second pole side of the second semiconductor chip. The first output terminal is connected to the second output terminal. A bus bar is connected to the second terminal and extends from the second terminal in a direction of the first surface on which the first terminal is provided.