A discrete power semiconductor package includes a semiconductor chip, a heatsink, a first lead, a second lead, and a clip. The heatsink is adjacent the semiconductor chip and draws heat away from the semiconductor chip. The clip binds the semiconductor chip to the heatsink and includes a chip linker, a first terminal, and a second terminal. The chip linker is atop the semiconductor chip. The first terminal connects to the first lead and the second terminal connects to the second lead.

A semiconductor device according to an embodiment includes a base frame, a semiconductor element provided on the base frame, a connector provided on the semiconductor element, the connector having an upper surface, a side surface, and a porous body having a plurality of pores provided on at least the side surface, and a molded resin provided in a periphery of the semiconductor element and at least the side surface of the connector. The upper surface of the connector is exposed.

According to one embodiment, a semiconductor device includes a package substrate including a package member and a first conductive portion; a semiconductor package provided on a first surface of the package substrate inside the package member and coupled to the first conductive portion; a first semiconductor chip provided on the first surface of the package substrate inside the package member and including a first terminal; a second semiconductor chip provided on the first surface of the package substrate inside the package member and including a second terminal; and a connection component that couples the first and second terminals to the first conductive portion inside the package member.

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.

A semiconductor device includes a semiconductor element and a conductive bond bonding the semiconductor element to a support. The semiconductor element has first to fourth sides, and the bond has first to fourth edges. Distance between the first side and the first edge in first direction is greater at ends than at the center of the first side in second direction crossing first direction. Distance between the second side and the second edge in first direction is greater at ends than at the center of the second side in second direction. Distance between the third side and the third edge in second direction is greater at ends than at the center of the third side in first direction. Distance between the fourth side and the fourth edge in second direction is greater at ends than at the center of the fourth side in first direction.

A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.

Provided is a semiconductor package including: at least one first substrate including at least one first substrate terminal extended therefrom; at least one second substrate joined to the upper surface of the first substrate using ultrasonic welding; at least one semiconductor chip joined to the upper surface of the second substrate; a package housing covering the at least one semiconductor chip and an area of the second substrate, where ultrasonic welding is performed; and terminals separated from the first substrate, electrically connected to the at least one semiconductor chip through electric signals, and at least one of them is exposed to the outside of the package housing, wherein a thickness of the terminals formed inside the package housing is same as or smaller than a thickness of the first substrate and the second substrate includes at least one embossing groove on the upper surface thereof.

Provided is a semiconductor module, including: a semiconductor chip; a terminal, configured to extend in a extending direction, and be connected electrically with the semiconductor chip; a sealing resin, configured to seal the semiconductor chip, and cover at least a part of an upper surface of the terminal and at least a part of a lower surface of the terminal; and a lower side resin, configured to extend in the extending direction from the sealing resin, and cover at least a part of the lower surface of the terminal, wherein in the extending direction, a length at which the sealing resin and the lower side resin cover the lower surface of the terminal is greater than a length at which the sealing resin covers the upper surface of the terminal in the extending direction; and wherein the sealing resin and the lower side resin are formed of a same material.