A semiconductor device includes: a seal portion; a first electronic element; a first lead terminal; a second lead terminal having one end that is disposed to be close to the one end of the first lead terminal within the seal portion, and another end that is exposed from another end of the seal portion, the other end of the seal portion being along the longitudinal direction; a first connecting element disposed within the seal portion, and having one end that is electrically connected to the first electrode disposed on the first electronic element, and another end that is electrically connected to the one end of the second lead terminal; and a conductive bonding agent.

A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

A semiconductor device includes a semiconductor element, leads, and an encapsulation resin covering a portion of each of the leads and the semiconductor element. Each of the leads includes an external connection portion projecting from a side surface of the encapsulation resin. The external connection portion of at least one of the leads has opposite ends in a width-wise direction that extends along the side surface of the encapsulation resin. The external connection portion includes two recesses arranged toward a center in the width-wise direction from the opposite ends. The two recesses extend from a distal surface toward the encapsulation resin. The opposite ends in the width-wise direction define an end connection part. The external connection portion includes a part between the two recesses defining a center connection part.

A semiconductor device according to the present disclosure includes a first semiconductor element; a first connecting member; and a first member. The first semiconductor element has a first element obverse surface and a first element reverse surface that face mutually opposite in a thickness direction. The first semiconductor element also has a first electrode disposed on the first element obverse surface. The first connecting member is electrically connected to the first electrode. The first member overlaps with the first electrode as viewed in the thickness direction, has a Vickers hardness lower than a Vickers hardness of the first connecting member, and has electroconductivity.

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.

A clip for a semiconductor package includes a first portion and a second portion. The first portion includes a first surface, a second surface opposite to the first surface and configured to contact a first electrically conductive component, and a stepped region between the first surface and the second surface such that the second surface has a smaller area than the first surface. The second portion is coupled to the first portion and configured to contact a second electrically conductive component. The second portion includes a third surface aligned with the first surface.

A semiconductor device includes: a seal portion; a first electronic element; a first lead terminal; a second lead terminal having one end that is disposed to be close to the one end of the first lead terminal within the seal portion, and another end that is exposed from another end of the seal portion, the other end of the seal portion being along the longitudinal direction; a first connecting element disposed within the seal portion, and having one end that is electrically connected to the first electrode disposed on the first electronic element, and another end that is electrically connected to the one end of the second lead terminal; and a conductive bonding agent.

A source pad electrically coupled with a source of a MOSFET of a semiconductor chip and located at a position below a lead in cross-sectional view is electrically connected with the lead for source via a conductive member bonded to the source pad and a wire bonded to the conductive member.

A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.