A method for producing a power semiconductor system includes packaging a power device in plastic to form a power semiconductor component, forming a first heat dissipation face on a surface of the power semiconductor component; heating a first material between a first heat sink and the first heat dissipation face; and cooling the first material on the first heat dissipation face to connect the power semiconductor component and the first heat sink.

A semiconductor device includes an insulation substrate including a circuit pattern, semiconductor chips mounted on the circuit pattern, a wire connecting between the semiconductor chips and between the semiconductor chip and the circuit pattern, and a conductive material serving as a conductor formed integrally with the wire.

A semiconductor device includes an insulation substrate including a circuit pattern, semiconductor chips mounted on the circuit pattern, a wire connecting between the semiconductor chips and between the semiconductor chip and the circuit pattern, and a conductive material serving as a conductor formed integrally with the wire.

Provided is a clip structure for a semiconductor package comprising: a first bonding unit bonded to a terminal part of an upper surface or a lower surface of a semiconductor device by using a conductive adhesive interposed therebetween, a main connecting unit which is extended and bent from the first bonding unit, a second bonding unit having an upper surface higher than the upper surface of the first bonding unit, an elastic unit elastically connected between the main connecting unit and one end of the second bonding unit, and a supporting unit bent and extended from the other end of the second bonding unit toward the main connecting unit, wherein the supporting unit is formed to incline at an angle of 1° through 179° from an extended surface of the main connecting unit and has an elastic structure so that push-stress applying to the semiconductor device while molding may be dispersed.

Provided is a clip structure for a semiconductor package comprising: a first bonding unit bonded to a terminal part of an upper surface or a lower surface of a semiconductor device by using a conductive adhesive interposed therebetween, a main connecting unit which is extended and bent from the first bonding unit, a second bonding unit having an upper surface higher than the upper surface of the first bonding unit, an elastic unit elastically connected between the main connecting unit and one end of the second bonding unit, and a supporting unit bent and extended from the other end of the second bonding unit toward the main connecting unit, wherein the supporting unit is formed to incline at an angle of 1° through 179° from an extended surface of the main connecting unit and has an elastic structure so that push-stress applying to the semiconductor device while molding may be dispersed.

A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

Provided is a semiconductor module including: a layered substrate on which a semiconductor chip is provided; and a connection terminal including a connection portion connected to the layered substrate, wherein the connection portion includes at least one ultrasonic connection section, and at least one laser-welded section, at least a portion of which is provided at a location other than a location at which the ultrasonic connection section is provided. The at least one ultrasonic connection section may be provided to be closer to the leading end of the connection portion than the at least one laser-welded section is.

Various embodiments may provide a semiconductor package. The semiconductor package may include a first electrical component, a second electrical component, a first heat sink, and a second heat sink bonded to a first package interconnection component and a second package interconnection component. The first package interconnection component and the second package interconnection component may provide lateral and vertical interconnections in the package.

Provided is a semiconductor module, including: a semiconductor chip including a semiconductor substrate and a metal electrode provided above the semiconductor substrate; a protective film provided above the metal electrode; a plated layer provided above the metal electrode, having at least a part being in a height identical to the protective film; a solder layer provided above the plated layer; and a lead frame provided above the solder layer, wherein the plated layer is provided in a range not in contact with the protective film.