A packaged device has a die of semiconductor material bonded to a support. An electromagnetic shielding structure surrounds the die and is formed by a grid structure of conductive material extending into the support and an electromagnetic shield, coupled together. A packaging mass embeds both the die and the electromagnetic shield. The electromagnetic shield is formed by a plurality of metal ribbon sections overlying the die and embedded in the packaging mass. Each metal ribbon section has a thickness-to-width ratio between approximately 1:2 and approximately 1:50.

LTCC structure extends between top and bottom surfaces, with at least one cavity being formed within the structure and extending from the top surface inwardly in the direction of the bottom surface. A die is disposed within the cavity a top surface of the die is positioned flush with the top surface of the package, resulted in the shortest length of the wire box connecting the die with the LTCC structure and ultimately reducing the inductance.

A method to connect power terminals to substrates within semiconductor packages is disclosed. The power terminal connection method minimally adapts the power terminal so that laser treatment can be used to connect the power terminal to the substrate. The power terminal may be adapted in a variety of ways, such that an interface between the power terminal and the substrate may be transformed (melted with consecutive rapid solidification) by the laser device, allowing the power terminal to be connected to the substrate.

A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a wide band-gap switch, a base plate, and a press device. The insulated gate bipolar transistor and the wide band-gap switch are connected in parallel and are each mounted with a first planar terminal to a side of the base plate. Further, a second planar terminal of the insulated gate bipolar transistor and a second planar terminal of the wind band-gap switch are connected with an electrically conductive connection element, and the press device is arranged on the second planar terminal of the insulated gate bipolar transistor. Hence, when arranging the semiconductor modules in a stack arrangement, any press force is primarily applied to the insulated gate bipolar transistors of the semiconductor modules.

A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation.

A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation.

A strip of semiconductor devices includes a plurality of leadframes electrically isolated from each other, a plurality of semiconductor chips, and an encapsulation material. Each leadframe has a first surface and a second surface opposite to the first surface. At least one semiconductor chip of the plurality of semiconductor chips is electrically coupled to the first surface of each leadframe. The encapsulation material encapsulates each semiconductor chip and at least portions of each leadframe.

A strip of semiconductor devices includes a plurality of leadframes electrically isolated from each other, a plurality of semiconductor chips, and an encapsulation material. Each leadframe has a first surface and a second surface opposite to the first surface. At least one semiconductor chip of the plurality of semiconductor chips is electrically coupled to the first surface of each leadframe. The encapsulation material encapsulates each semiconductor chip and at least portions of each leadframe.

A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.

A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.