A power module includes a plurality of conductive wire groups and a sealing member. The plurality of conductive wire groups each include a first bonded portion and a second bonded portion. A maximum gap between intermediate portions of a pair of conductive wire groups adjacent to each other is larger than a first gap between the first bonded portions of the pair of conductive wire groups adjacent to each other. The maximum gap between the intermediate portions of the pair of conductive wire groups adjacent to each other is larger than a second gap between the second bonded portions of the pair of conductive wire groups adjacent to each other. Therefore, the power module is improved in reliability.

A power module includes a plurality of conductive wire groups and a sealing member. The plurality of conductive wire groups each include a first bonded portion and a second bonded portion. A maximum gap between intermediate portions of a pair of conductive wire groups adjacent to each other is larger than a first gap between the first bonded portions of the pair of conductive wire groups adjacent to each other. The maximum gap between the intermediate portions of the pair of conductive wire groups adjacent to each other is larger than a second gap between the second bonded portions of the pair of conductive wire groups adjacent to each other. Therefore, the power module is improved in reliability.

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.

There is provided a copper bonding wire having an improved storage life in the atmosphere. There is specifically provided a copper bonding wire for semiconductor devices characterized in that a density of crystal grain boundary on a surface of the wire is 0.6 (μm/μm.sup.2) or more and 1.6 (μm/μm.sup.2) or less.

There is provided a copper bonding wire having an improved storage life in the atmosphere. There is specifically provided a copper bonding wire for semiconductor devices characterized in that a density of crystal grain boundary on a surface of the wire is 0.6 (μm/μm.sup.2) or more and 1.6 (μm/μm.sup.2) or less.

A semiconductor power module comprises an insulating interposer comprising an insulative layer disposed between a lower metal layer, a first upper metal layer and a second upper metal layer, a semiconductor transistor die disposed on the first upper metal layer, an electrical connector connecting the semiconductor transistor die with the second upper metal layer, a housing enclosing the insulating interposer and the semiconductor transistor die, a first potting material covering at least selective portions of the semiconductor transistor die and the electrical connector; and a second potting material applied onto the first potting material, wherein the first and second potting materials are different from each other.

A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.

A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.

Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.