A metallic ribbon for power module packaging is described. The metallic ribbon has a rectangular, oval or oblong cross section. The composition of the metallic ribbon is silver-palladium alloy containing 0.2 to 6 wt % Pd. The metallic ribbon has a thickness of 10 m to 500 m. The width of the metallic ribbon is 2 to 100 times its thickness. The metallic ribbon includes a plurality of grains. The average grain size of the grains observed in the transverse cross section is 2 m to 10 m. The metallic ribbon has a plurality of twin grains observed in the transverse cross section, and the number of twin grains observed in the transverse cross section accounts for at least 5% of the total number of grains observed in the transverse cross section.

A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.

A process for manufacturing a bonding wire containing a core having a surface. The core contains 98.0% copper and has a cross sectional area of 75,00 to 600,000 m.sup.2 and an elastic limit RP0.2 (yield strength) of 40 to 95 N/mm.sup.2. The process involves (a) providing a copper core precursor; (b) drawing the precursor until a final diameter of the wire core is reached; and (c) annealing the drawn wire at a minimum annealing temperature of 650 to 1000 C. through its entire cross section for a minimum annealing time of 4 seconds to 2 hours.

A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.