A system includes a substrate; a bond pad; a wire spanning above the substrate, having a first end bonded to the bond pad and a second end extending from the bond pad to terminate in a second end thereof; and a support structure disposed on the substrate, the support structure comprising at least a side wall and extending from the substrate to terminate in an end portion spaced from the substrate to support the wire.

A semiconductor device, including an insulated circuit board that has a radiation plate, a resin board adhered to a front surface of the radiation plate, and a circuit pattern adhered to a front surface of the resin board. The resin board contains a resin. The semiconductor device further includes a wiring member, and at least one semiconductor chip, bonded to the front surface of the circuit pattern or electrically connected to the wiring member. The circuit pattern has at least one pair of side portions opposite to each other that are supported by the resin board.

A semiconductor device, including an insulated circuit board that has a radiation plate, a resin board adhered to a front surface of the radiation plate, and a circuit pattern adhered to a front surface of the resin board. The resin board contains a resin. The semiconductor device further includes a wiring member, and at least one semiconductor chip, bonded to the front surface of the circuit pattern or electrically connected to the wiring member. The circuit pattern has at least one pair of side portions opposite to each other that are supported by the resin board.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

A semiconductor module includes: an insulating heat dissipation sheet; a semiconductor device provided on the heat dissipation sheet; a lead frame including a lead terminal and a die pad which are formed integrally; a wire connecting the lead frame to the semiconductor device and constituting a main current path; and a mold resin scaling the heat dissipation sheet, the semiconductor device, the lead frame and the wire, wherein the lead terminal is led out from the mold resin, the heat dissipation sheet is in direct contact with an undersurface of the die pad, and the wire is bonded to the die pad directly above a contact part provided between the die pad and the heat dissipation sheet.

An intelligent power module (IPM) comprises a first, second, third and fourth die supporting elements, a first group of insulated gate bipolar transistors (IGBTs), a second group of IGBTs, a first group of super-junction metal-oxide-semiconductor field-effect transistors (MOSFETs), a second group of super-junction MOSFETs, a fifth die supporting element, a low voltage IC, a high voltage IC, and a molding encapsulation. The low and high voltage ICs are attached to the fifth die supporting element. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first group of IGBTs, the second group of IGBTs, the first group of super-junction MOSFETs, the second group of super-junction MOSFETs, the fifth die supporting element, the low voltage IC, the high voltage IC.

An intelligent power module (IPM) comprises a first, second, third and fourth die supporting elements, a first group of insulated gate bipolar transistors (IGBTs), a second group of IGBTs, a first group of super-junction metal-oxide-semiconductor field-effect transistors (MOSFETs), a second group of super-junction MOSFETs, a fifth die supporting element, a low voltage IC, a high voltage IC, and a molding encapsulation. The low and high voltage ICs are attached to the fifth die supporting element. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first group of IGBTs, the second group of IGBTs, the first group of super-junction MOSFETs, the second group of super-junction MOSFETs, the fifth die supporting element, the low voltage IC, the high voltage IC.