A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.

Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.

Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode.

A printed circuit board includes first and second insulating layers forming a cavity, a first heat releasing layer formed on an exterior surface of the cavity, and a circuit layer formed above or below the first the insulating layer and at least between a surface of the cavity and the first insulating layer. The heat releasing layer is electrically connected to at least a portion of the circuit layer.

In a general aspect, a chip-on-lead semiconductor device package can include a leadframe having a plurality of signal leads. The plurality of signal leads can include at least two signal leads each having a first face with a first surface area and, opposite the first face, a second face with a second surface area, the second faces of the at least two signal leads being exposed on a surface of the chip-on-lead device package. The plurality of signal lead can also include at least one signal lead having a first face with a third surface area and, opposite the first face of the at least one signal lead, a second face with the second surface area, the second face of the at least one signal lead being exposed on the surface of the chip-on-lead semiconductor device package.

A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin.

A connecting member includes a first part arranged between a first region of an electronic device and a board and a second part arranged between a second region of the electronic device and the board, a distance from an edge to the first part is longer than a distance from a center to the first part, and a distance from the edge to the second part is shorter than a distance from the center to the second part, a space is provided between the electronic device and the board and between the first part and the second part, and, in the board, a through hole communicating with the space is provided not to overlap with the center of the electronic device.

An optical device includes: an optical element that is rectangular as seen in a top view, and that has a light-receiving portion at a top surface thereof; a wiring substrate on which the optical element is mounted; wires electrically connecting the optical element and the wiring substrate at from one to three sides of the rectangular optical element; a resin portion formed at a periphery of the optical element, and covering a portion of the top surface of the optical element including the wires; and an opening portion that is concave, that is provided in the resin portion, and that is formed by a molding die such that at least the light-receiving portion and the top surface at a periphery of the light-receiving portion are exposed, wherein the resin portion that structures a bottom surface at the opening portion is flush with the top surface.