An electronic system is disclosed. The electronic system includes an electronic package having a base with a plurality of external terminals, and further having an electrically insulative material at least partially encapsulating the base, a controller circuit disposed within the electronic package and referenced to a first ground, a first and second driver circuits disposed within the electronic package and referenced to a second ground and arranged to receive isolated control signals from the controller circuit, and a bidirectional switch disposed within the electronic package and referenced to the second ground and arranged to receive drive signals from the first and second driver circuits. In one aspect, the first and second driver circuits are isolated from the controller circuit via capacitors, or magnetics, or optocouplers, or magneto resistors.

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

A semiconductor package structure includes a base. A first die is mounted on the base. The first die includes a plurality of first pads arranged in a first tier, and a plurality of second pads arranged in a second tier. A second die is mounted on the base and includes a plurality of third pads with the first pad area, and a plurality of fourth pads with the second pad area, alternately arranged in a third tier. The second die also includes a first bonding wire having two terminals respectively coupled to one of the first pads and one of the fourth pads. The semiconductor package structure also includes a second bonding wire having two terminals respectively coupled to one of the third pads and one of the second pads.

A semiconductor module arrangement includes a substrate including a dielectric insulation layer and a first metallization layer arranged on a surface of the dielectric insulation layer, wherein the first metallization layer comprises a first section, a second section, and a third section, and a first semiconductor body and an identical second semiconductor body arranged on the first metallization layer, wherein each of the first semiconductor body and the second semiconductor body has a first contact pad, a second contact pad, and a third contact pad arranged on a top side of the respective semiconductor body that faces away from the substrate, wherein the third contact pad of the first semiconductor body is electrically coupled to the third section of the first metallization layer by means of a first electrical connection element, the third contact pad of the second semiconductor body is electrically coupled to the third section of the first metallization layer by means of a second electrical connection element, the semiconductor module arrangement further includes at least one third terminal element arranged on the third section, a first current path between the third contact pad of the first semiconductor body and the at least one third terminal element provides identical voltage and current transfer characteristics as a second current path between the third contact pad of the second semiconductor body and the at least one third terminal element, and each of the first and second electrical connection elements includes one or more bonding wires, one or more bonding ribbons, a connection rail, or a section of an additional metallization layer of the substrate that is contacted by corresponding vias.

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

A bonding wire includes a wire core including a silver-palladium alloy, and a coating layer disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.

A semiconductor apparatus includes (i) semiconductor chips including a power semiconductor chip including a switch and a control semiconductor chip including a control circuit configured to control the switch, (ii) redistribution layers including a first redistribution layer that electrically connects a first semiconductor chip to a second semiconductor chip from among the semiconductor chips, (iii) a first sealing material that seals the semiconductor chips and the redistribution layers, (iv) an insulating substrate including a first conductor layer, a second conductor layer and an insulating layer between the first and second conductor layers, in which the insulating substrate is fixed to the first sealing material to be opposed to the semiconductor chips and the redistribution layers, and (v) a second sealing material that seals the insulating substrate and the first sealing material.

A semiconductor device according to an embodiment includes a substrate, a plurality of first semiconductor chips, a plurality of first resins, and a second semiconductor chip. The substrate has a first surface. The plurality of first semiconductor chips are stacked while being displaced in a direction substantially parallel to the first surface. The plurality of first resins are provided on respective lower surfaces of the plurality of first semiconductor chips. The second semiconductor chip is provided on the first surface. At least one of the plurality of first resins is in contact with an upper surface of the second semiconductor chip.

An electronic device includes: an electronic component; a sealing resin covering the electronic component; a first lead including a first inner portion and a first outer portion; a second lead including a second inner portion and a second outer portion; and a wire including a bonding segment secured to the first inner portion and a bonding segment secured to the second inner portion. The first inner portion is located inside a peripheral edge of the sealing resin as viewed in a thickness direction z, except at a first boundary with the first outer portion. The second inner portion is located inside the peripheral edge of the sealing resin as viewed in the thickness direction z, except at a second boundary with the second outer portion. As viewed in the thickness direction z, the wire has a length that is at least 25% of an average of a distance from the first boundary to the bonding segment secured to the first inner portion and a distance from the second boundary to the bonding segment secured to the second inner portion.

A package structure including a substrate, a first lead frame, a first metal layer, at least one chip, a base and a second metal layer is provided. The base includes a plurality of openings. The first lead frame is embedded in the substrate and includes a plurality of first pads, where the openings expose the first pads. The first metal layer covers the exposed first pads. The chip is disposed on the substrate and electrically connected to the first metal layer and the first pads. The base covers the substrate with its bonding surface. The second metal layer covers a base surface of the base.