Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.

A semiconductor device, including a circuit pattern, a contact part and an external connection terminal. The contact part has a cylindrical through-hole and first and second opening ends opposite to each other, the second opening end being joined to the circuit pattern. The external connection terminal has a prismatic main body portion and first and second end portions, the second end portion being inserted into the through-hole from the first opening end of the contact part. The main body portion of the external connection terminal has an insertion prevented portion formed thereon. The contact part includes an insertion preventing portion formed on an inner circumferential surface of the through-hole, the insertion preventing portion being so positioned as to be substantially downstream, with respect to an insertion direction of the external connection terminal, from the main body portion of the external connection terminal inserted into the through-hole.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.

A power module includes a substrate that is electrically insulative and includes a substrate main surface and a substrate back surface at opposite sides in a thickness direction. The power module also includes a mounting layer that is conductive and arranged on the substrate main surface. The power module further includes a graphite plate having anisotropic thermal conductivity and including a plate main surface and a plate back surface at opposite sides in the thickness direction. The plate back surface is connected to the mounting layer. The power module further includes a power semiconductor element arranged on the plate main surface.

A connecting strip of conductive elastic material having an arched shape having a concave side and a convex side. The connecting strip is fixed at the ends to a support carrying a die with the convex side facing the support. During bonding, the connecting strip undergoes elastic deformation and presses against the die, thus electrically connecting the at least one die to the support.

A semiconductor module includes first and second switching devices and first and second control devices all sealed in a package rectangular in a plan view, signal terminals on a side surface of a first long side input signals to the first and second control devices, each of the first and second switching devices outputs one of the signals from an output terminal on a side surface of a second long side, each of the first and second control devices includes a control ground connected to a control ground terminal on the side surface of the first long side, a main power terminal and a power ground terminal are disposed on the side surface of the second long side, and the power ground terminal is electrically connected inside the package to the control ground terminal through a current detection resistor outside the package and an impedance component inside the package.

A semiconductor package includes a mounting platform including an electrically insulating substrate and structured metallization layers, a semiconductor die mounted on an upper surface of the mounting platform, the semiconductor die including a first terminal and a second terminal, the first terminal disposed on a second surface of the semiconductor die that faces the mounting platform, the second terminal disposed on a first surface of the semiconductor die that faces away from the mounting platform, and a heat sink integrally formed in the mounting platform. The heat sink is directly underneath the semiconductor die and is thermally coupled to the semiconductor die. The heat sink extends from the upper surface of the mounting platform to a lower surface of the mounting platform. The heat sink includes one or more discrete metal blocks disposed within an opening formed in the electrically insulating substrate.

A switching module includes at least one substrate, at least one switching element, at least one control loop, a first power part and a second power part. The at least one switching element is disposed on the at least one substrate. The at least one control loop is connected with the corresponding switching element. The first power part is connected with the corresponding switching element. The second power part is connected with the corresponding switching element. A direction of a first current flowing through the first power part and a direction of a second current flowing through the second power part are identical. A projection of the first power part on a reference plane and a projection of the second power part on the reference plane are located at two opposite sides of a projection of the control loop on the reference plane.

A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.