Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/42
Wire connectors; Manufacturing methods related thereto
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H01L2224/47
Structure, shape, material or disposition of the wire connectors after the connecting process
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H01L2224/48
of an individual wire connector
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H01L2224/48135
Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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H01L2224/48137
the bodies being arranged next to each other, e.g. on a common substrate
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H01L2224/4814
the wire connector connecting to a bonding area protruding from the surface
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H01L2224/4814

PACKAGE COMPRISING INTEGRATED DEVICES AND WIRE BONDS COUPLED TO INTEGRATED DEVICES
20250293197 · 2025-09-18 ·

A package comprising a substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; and a plurality of wire bonds coupled to the first integrated device and the second integrated device.

SEMICONDUCTOR DEVICE
20250309178 · 2025-10-02 ·

A semiconductor device includes a first semiconductor element, a second semiconductor element, a first lead, a second lead, a first wire, and a first bump-stacked body. The first lead is electrically connected to the first semiconductor element. The second lead is electrically connected to the second semiconductor element and is separated from the first lead. The first wire electrically connects the first semiconductor element and the second semiconductor element. The bump-stacked body includes a plurality of bumps stacked in a thickness direction of the first semiconductor element. The first wire includes a first end overlapping with the first semiconductor element and a second end overlapping with the second semiconductor element in the thickness direction. The first bump-stacked body is located between the first semiconductor element and the first end or between the second semiconductor element and the second end.

ISOLATION CHIP AND METHOD FOR MANUFACTURING ISOLATION CHIP
20250357434 · 2025-11-20 · ·

An insulation chip includes a substrate, a first insulator, a first conductor, a second insulator, and a second conductor. The first conductor is embedded in the first insulator and exposed from the first insulator. The second insulator covers the first insulator and the first conductor. The second conductor is disposed on the second insulator. The first conductor, which includes an electrode pad, and the second conductor face each other in a thickness direction perpendicular to the upper surface of the first insulator. The second insulator includes insulating layers arranged on the first insulator and an exposing recess extending through the insulating layers to expose the electrode pad. The wall of the exposing recess is stepped such that the distance to the electrode pad increases from the upper surface of the first insulator toward the upper surface of the second insulator.