A package substrate may include first conductive patterns, a first insulation layer and a second insulation layer. The first conductive patterns may be electrically connected with a semiconductor chip. The first insulation layer may be on an upper surface and side surfaces of each of the first conductive patterns. The first insulation layer may include at least one opening under at least one of side surfaces of the semiconductor chip. The second insulation layer may be on a lower surface of each of the first conductive patterns. Thus, a gas generated from the DAF may be readily discharged through the opening. A spreading of a crack, which may be generated at the interface between the side surface of the semiconductor chip and the molding member, toward the conductive patterns of the package substrate may be limited and/or suppressed. Adhesion between the semiconductor chip and the molding member may be reinforced.

A semiconductor package includes a package substrate, a die stack having a first sub-stack part and a second sub-stack part, an interface chip, and a bonding wire structure. The bonding wire structure includes a first signal wire connecting first signal die pads included in the first sub-stack part to each other, a first signal extension wire connecting the first signal wire to the interface chip, a second signal wire connecting second signal die pads included in the first sub-stack part to each other, a second signal extension wire connecting the second signal wire to the interface chip, an interpose wire connecting interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads to the interface chip, and a shielding wire branched from the interpose wire.

A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.

Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.

A memory device includes a substrate, a three-dimensional (3D) NAND memory cell array on the substrate, and a peripheral circuit including a transistor on the substrate. The substrate includes p-type impurities and n-type impurities, a concentration of the n-type impurities in the substrate is lower than a concentration of the p-type impurities in the substrate, and the concentration of the n-type impurities in the substrate is about 2×10.sup.14 atoms/cm.sup.3 to about 1.5×10.sup.15 atoms/cm.sup.3 while the concentration of the p-type impurities in the substrate is about 9×10.sup.14 atoms/cm.sup.3 to about 2×10.sup.15 atoms/cm.sup.3.

A semiconductor package includes a package substrate, first and second semiconductor chips stacked on the package substrate and wire-bonded to the package substrate. The first semiconductor chip includes first differential pair signal pads, a first option signal pad, and a first signal path control circuit. The second semiconductor chip includes second differential pair signal pads, a second option signal pad, and a second signal path control circuit. The first signal path control circuit changes a signal path of one of the differential pair signals of the first semiconductor chip by a first control signal. The second signal path control circuit changes a signal path of one of the differential pair signals of the second semiconductor chip by a second control signal.

A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current.

Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.

A semiconductor package includes a substrate; a sub semiconductor package disposed over the substrate, the sub semiconductor package including a sub semiconductor chip with chip pads on its active surface that faces the substrate, a sub molding layer that surrounds side surfaces of the sub semiconductor chip, the sub molding layer with a surface that faces the substrate, and redistribution conductive layers that connect to the chip pads and extend under the surface of the sub molding layer, wherein the redistribution conductive layers include a signal redistribution conductive layer that extends toward an edge of the sub molding layer, the signal redistribution conductive layer with a signal redistribution pad on its end portion, and a power redistribution conductive layer that has a length that is shorter than a length of the signal redistribution conductive layer, the power redistribution conductive layer with a power redistribution pad on its end portion; a signal sub interconnector with an upper surface that is connected to the signal redistribution pad and a lower surface that is connected to the substrate; a power sub interconnector with an upper surface that is connected to the power redistribution pad and a lower surface that is connected to the substrate; and at least one main semiconductor chip formed over the sub semiconductor package and electrically connected to the substrate.

A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.