An optical coupling module includes a silicon photonic substrate, and an optical waveguide module. The silicon photonic substrate has a first surface and a first grating on the first surface for diffracting the light which passes through the grating. The optical waveguide module is disposed on the silicon photonic substrate, wherein the optical waveguide module includes an optical waveguide having an end disposed in corresponding to the first grating of the silicon photonic substrate. Otherwise, the optical waveguide module has a reflective surface coupled to the end of the optical waveguide and adapted to reflect the light emerging from or incident into the grating to form an optical path between the silicon photonic substrate and the optical waveguide for transmitting the light.

A display apparatus includes a display panel and a display panel driver. The display panel includes a first substrate and a second substrate facing the first substrate, wherein the first substrate includes a switching element, a data line and a gate line, wherein the data line and the gate line are electrically connected to the switching element. The display panel driver includes a data driving chip and a gate driving chip, wherein the data driving chip applies a data signal to the data line and the gate driving chip applies a gate signal to the gate line, wherein the gate driving chip is disposed on a surface of the data driving chip.

A fingerprint sensing device comprising sensing circuitry comprising a plurality of sensing elements, each sensing element comprising a sensing structure arranged in a sensing plane and facing a surface of the capacitive fingerprint sensing device, each of the sensing elements being configured to provide a signal indicative of an electromagnetic coupling between the sensing structure and a finger placed on the surface of the fingerprint sensing device; and a plurality of connection pads electrically connected to the sensing circuitry for providing an electrical connection between the sensing circuitry and readout circuitry, wherein each of the connection pads is separately recessed in relation to the sensing plane such that each connection pad has a floor in a floor plane, and wherein each connection pad is separated from an adjacent connection pad through a portion of the sensing device being elevated in relation to the floor plane.

A semiconductor device may include a peripheral circuit structure first bonding pads connected to peripheral circuits on a semiconductor substrate; and a cell array structure including second bonding pads bonded to the first bonding pads. The cell array structure may include a separation structure penetrating a stack structure, vertical channel patterns penetrating the stack structure, a source conductive pattern connected to the vertical channel patterns on the stack structure, an upper dielectric layer covering the source conductive pattern, and an upper via that penetrates the upper dielectric layer. The stack structure may include interlayer dielectric layers and conductive patterns that are vertically alternately stacked. The separation structure may include a stop pattern on a dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern. The upper via may connect to the source conductive pattern on the stop pattern.

A molded surface mount package includes: a power semiconductor die attached to a metallic pad with a first side facing the pad and a second (opposite) side facing away from the pad, the metallic pad forming a first power terminal exposed at a surface mounting side of the package; a second power terminal, a first sense terminal, and a gate terminal each exposed at the surface mounting side and spaced apart from the first power terminal; a first electrical connection between the second power terminal and a first power pad at the second side of the die; a second electrical connection between the gate terminal and a gate pad at the second side of the die; a third electrical connection between the first sense terminal and a first sense pad at the second side of the die; and a first redundant electrical connection for the second or third electrical connection.

A semiconductor package includes a substrate extending in a first direction and a second direction perpendicular to the first direction, a first semiconductor chip disposed on the substrate, the first semiconductor chip having a stepped portion, a second semiconductor chip disposed on the substrate and horizontally spaced apart from the first semiconductor chip in the first direction, a third semiconductor chip disposed on the second semiconductor chip and a bottom surface of the stepped portion, and an upper adhesive layer disposed between the second semiconductor chip and the third semiconductor chip, the upper adhesive layer contacting a portion of the bottom surface of the stepped portion.

A semiconductor package includes a package substrate including an insulating layer, an interconnection circuit, and upper pads and lower pads electrically connected through the interconnection circuit, a plurality of semiconductor chips stacked including connection pads, a support structure contacting a side surface of a first semiconductor chip, which is an uppermost one among the plurality of semiconductor chips and at least a portion of an upper surface of a second semiconductor chip, which is one among the plurality of semiconductor chips below the first semiconductor chip, a first connection structure connecting the upper pads of the package substrate to the connection pads of the second semiconductor chip, a second connection structure connecting the connection pads of the first semiconductor chip to the connection pads of the second semiconductor chip, and an encapsulant covering the plurality of semiconductor chips, the first connection structure, and the second connection structure.

A semiconductor package may include: a substrate having a first side and a second side on a same plane; a first semiconductor chip disposed over the second side of the substrate; a first one-side third semiconductor chip stack disposed over the first side of the substrate and spaced apart from the first semiconductor chip; a second semiconductor chip stack disposed over the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second one-side third semiconductor chip stack disposed over the second semiconductor chip stack, wherein each of the third semiconductor chip stacks includes a plurality of third semiconductor chips that are offset-stacked, offset towards the first side as the third semiconductor chips are farther from the substrate, each of the third semiconductor chip stacks being electrically connected to the substrate.

A semiconductor package including a first semiconductor chip, which includes a first semiconductor board, a bonding pad on the first semiconductor board, and a protection layer covering an upper surface of the first semiconductor board and including a recessed region exposing at least a portion of an upper surface of the bonding pad therethrough, a second semiconductor chip including a second semiconductor board in direct contact with the protection layer, and a wire electrically connecting the first semiconductor chip and the second semiconductor chip and connected to the bonding pad may be provided.

A semiconductor package includes at least one internal temperature sensor to detect an operating temperature of the semiconductor package. The operating temperature is based on a surface temperature of an enclosure of the semiconductor package. As such, the at least one internal temperature sensor is positioned within a cavity defined by the enclosure to measure the temperature of the enclosure. The at least one internal temperature sensor can be coupled to an inner side of the enclosure or it can be proximate to the enclosure. Temperature measurements provided by the at least one internal temperature sensor are used to determine whether the semiconductor package is operating within operating temperature ranges specified by one or more standards.