In a general aspect, a semiconductor device assembly includes a substrate having a patterned metal layer disposed thereon, a first semiconductor die, the first semiconductor die disposed on a first portion of the patterned metal layer, and a second semiconductor die disposed on the first portion of the patterned metal layer. The assembly also includes a first electrical connection electrically coupling a second portion of the patterned metal layer with the first semiconductor die. and a second electrical connection electrically coupling the second portion of the patterned metal layer with the second semiconductor die. The second electrical connection is substantially electrically balanced with the first electrical connection.

A semiconductor device includes a first semiconductor chip, a die attach film, a second semiconductor chip, and a resin molding member. The first semiconductor chip is attached to the second semiconductor chip via the die attach film. The second semiconductor chip includes an analog circuit, a bonding pad, and one or more deformed bonding pads serving as alignment marks of the first semiconductor chip. In plan view, the analog circuit is located inside an outer peripheral edge of the die attach film. The resin molding member seals the first semiconductor chip, the second semiconductor chip, and the die attach film.

A method of manufacturing a semiconductor device is provided. The method includes attaching a first die pad of a semiconductor die to a central pad of a package leadframe. The first die pad is located in a central region on an active side of the semiconductor die. A second die pad of the semiconductor die is connected a lead of the package lead frame. The second die pad is located in a periphery region on the active side of the semiconductor die. An encapsulant encapsulates a portion of the semiconductor die and a portion of the package leadframe. A backside surface of the semiconductor die is exposed at a top major surface of the encapsulant, and a backside surface of the central pad exposed at a bottom major surface of the encapsulant.

A semiconductor device includes a wiring substrate inside which a wiring layer is provided, a plurality of first semiconductor chips stacked in a shifted manner on the wiring substrate and each provided with a connection terminal on a surface facing the wiring substrate, and a second semiconductor chip having a function different from functions of the first semiconductor chips and provided on the wiring substrate on a side where the connection terminals are electrically connected to the wiring substrate.

A semiconductor package including a substrate and at least one semiconductor chip on the substrate may be provided. The substrate may include a body layer having a top surface and a bottom surface, a first thermal conductive plate on the top surface of the body layer, the first thermal conductive plate connected to a ground terminal of the semiconductor chip, and a thermal conductive via penetrating the body layer and being in contact with the first thermal conductive plate.

A semiconductor package includes first bump structures that include a stud portion disposed below the second rear surface pads of the first group, and a bonding wire portion that extends from the stud portion and is connected to the first front surface pads of the first group; second bump structures disposed below the second rear surface pads of the second group; an encapsulant that encapsulates the second semiconductor chip and the first and second bump structures; and a redistribution structure disposed below the encapsulant, and that includes an insulating layer, redistribution layers disposed below the insulating layer, and redistribution vias that penetrate through the insulating layer and connect the redistribution layers to the first bump structures or the second bump structures. At least a portion of the redistribution vias connected to the first bump structures is in contact with the stud portion.

A semiconductor package includes a base substrate, a first semiconductor chip, a second semiconductor chip, a first voltage bonding wire, a second voltage bonding wire and a first capacitance-sharing bonding wire. The base substrate includes substrate pads. The first semiconductor chip is stacked on the base substrate in a vertical direction and includes first chip pads. The second semiconductor chip is stacked on the first semiconductor chip in the vertical direction and includes second chip pads. The first voltage bonding wire electrically connects a first substrate voltage pad of the substrate pads and a first chip voltage pad of the first chip pads. The second voltage bonding wire electrically connects a second substrate voltage pad of the substrate pads and a second chip voltage pad of the second chip pads. The first capacitance-sharing bonding wire electrically connects the first chip voltage pad and the second chip voltage pad.

A semiconductor device includes: a first transformer; a second transformer; a first rectifier chip; a second rectifier chip; and a first frame. Each of the first rectifier chip and the second rectifier chip includes: a first output pad and a second output pad; a semiconductor substrate of a first conductivity type including a first surface; a first semiconductor region of a second conductivity type disposed on the first surface; a first transistor provided in the first semiconductor region and electrically connected to the first output pad; and a second semiconductor region of the second conductivity type provided at a position spaced apart from the first transistor in the first semiconductor region and electrically connected to the second output pad. The second semiconductor region is in contact with the semiconductor substrate. The first rectifier chip and the second rectifier chip are disposed to be spaced apart from each other.

A semiconductor package includes a package substrate having a first side portion adjacent to a first edge, and a second side portion adjacent to a second edge opposite the first edge; a plurality of first substrate pads on the package substrate at the first side portion of the package substrate; a first chip on the package substrate; a second chip stacked on the first chip in a step-wise manner to result in a first exposure region exposing a portion of a surface of the first chip with respect to the second chip due to the step-wise stacking, the first exposure region being adjacent to a first edge of the first chip; a plurality of first bonding pads on a first portion of the first exposure region, the first portion of the first exposure region being adjacent to the first edge of the first chip; a plurality of second bonding pads on a second portion of the first exposure region, the second portion of the first exposure region further from the first edge of the first chip than the first portion of the first exposure region is to the first edge of the first chip, the plurality of second bonding pads being electrically insulated from any circuit components in the first chip; a plurality of third bonding pads on a surface of the second chip; and a plurality of bonding wires electrically connecting the third bonding pads to the first substrate pads via the second bonding pads.