In a circuit substrate, a plurality of first microstrip lines connect outputs of a plurality of circuit patterns containing a parallel capacitor to a plurality of first output pads respectively. A plurality of second wires connect the first output pads of the circuit substrate to inputs of a plurality of transistor cells of a semiconductor substrate respectively. The numbers of the fingers of the transistor cells are the same. The first microstrip lines connected to the circuit patterns disposed on both sides of the lining-up circuit patterns are longer than the other first microstrip lines.

A semiconductor device includes a first semiconductor element, a first terminal electrically connected to the first semiconductor element, a second terminal electrically connected to the first semiconductor element and spaced apart from the first terminal in a first direction, and a sealing resin covering the first semiconductor element and a part of each of the first terminal and the second terminal. The sealing resin includes a first side surface facing in a second direction orthogonal to the first direction and located closest to the first terminal and the second terminal in the second direction. The first terminal and the second terminal are spaced apart from the first side surface.

Provided is a semiconductor device that reduces stress generated in a capacitor due to temperature changes in the semiconductor device, thereby suppressing damage to the capacitor. The semiconductor device includes an insulating substrate, a semiconductor element, a capacitor, a first lead having a surface, and a second lead having a surface, in which the insulating substrate includes an insulating layer and a conductor pattern provided on the insulating layer, the semiconductor element is bonded onto the conductor pattern, the first lead is electrically connected to the semiconductor element, the surface of the first lead and the surface of the second lead face each other, the capacitor is positioned between the surface of the first lead and the surface of the second lead facing each other, and the capacitor is connected to the first lead and the second lead.

A power module is designed with balanced current flow for each power switch in parallel so that every power switch has a similar current path length. The power module can include a first plurality of power switches electrically coupled to a first region and a second plurality of power switches electrically coupled to a second region. A first plurality of conductive clips are configured to conduct a first plurality of currents and a second plurality of conductive clips are configured to conduct a second plurality of currents. The power module can include a first lead frame configured to apply positive voltage to the first region, a second lead frame configured to conduct current from the second region and a third lead frame configured to conduct current from the third region.

In a circuit substrate, a plurality of first microstrip lines connect outputs of a plurality of circuit patterns containing a parallel capacitor to a plurality of first output pads respectively. A plurality of second wires connect the first output pads of the circuit substrate to inputs of a plurality of transistor cells of a semiconductor substrate respectively. The numbers of the fingers of the transistor cells are the same. The first microstrip lines connected to the circuit patterns disposed on both sides of the lining-up circuit patterns are longer than the other first microstrip lines.

A semiconductor device includes: an insulated circuit board including an insulating plate and a conductive layer provided on a top surface side of the insulating plate; a semiconductor chip provided on a top surface side of the conductive layer; a sealing resin sealing the semiconductor chip; and an external terminal electrically connected to the semiconductor chip and having a lower portion embedded in the sealing resin and an upper portion projecting above a top surface of the sealing resin.

Provided is a method of processing a NAND flash memory device including at least one NAND flash memory and a memory controller configured to control the at least one NAND flash memory. The method includes etching a portion of a first substrate of the NAND flash memory device to expose a wire connecting the at least one NAND flash memory and the memory controller to each other, dividing the wire into a first wire and a second wire by etching a first area of the etched first substrate, and connecting, to a second substrate, the first wire to which the at least one NAND flash memory is connected.

A semiconductor device, including: a stacked substrate; a plurality of semiconductor chips provided on the stacked substrate; an external output terminal; a circuit board configured to electrically connect the plurality semiconductor chips, and to electrically connect the plurality of semiconductor chips to the external output terminal, the circuit board having a first surface and a second surface opposite to each other, the second surface facing the stacked substrate; a sealing resin sealing the stacked substrate and the circuit board; and a plurality of flow velocity control pins attached to the circuit board, at the first surface of the circuit board.

A semiconductor device including a first substrate including a first insulating substrate, a first wiring pattern layer and first front-side pads formed on a front surface of the first insulating substrate, and a first base portion constituted by thick copper on a back surface thereof, a first semiconductor element fixed to the first substrate via a first heat sink in a first opening of the first insulating substrate, a second substrate including a second insulating substrate, a second wiring pattern layer and second front-side pads formed on a front surface of the second insulating substrate, and a second base portion constituted by thick copper on a back surface thereof, a second semiconductor element fixed to the second substrate via a second heat sink in a second opening of the second insulating substrate, and a third substrate arranged between the first substrate and the second substrate to face them.

A semiconductor packaging structure includes a copper heat-sink with a shim projection which provides a stress release structure. The heat-sink with the shim projection may be used in conjunction with a pedestal in order to further reduce the thermal stress produced from the mismatch of thermal properties between the copper heat-sink metal and the ceramic frame. The copper heat-sink with a shim projection may also be part of the semiconductor package along with a lead frame, the ceramic frame, a semiconductor device, a capacitor, a wire bond and a ceramic lid or an encapsulation. The copper heat-sink, the ceramic frame and the lead frame are all chosen to be cost effective, and chosen such that the packaging process for the semiconductor device is able to achieve a smaller size while maintaining high reliability, low cost, and suitability for volume manufacturing.