An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

A multi-chip package may include a package substrate including a first substrate pad and a second substrate pad, first semiconductor chips stacked on the package substrate in a steplike shape along a first direction, second semiconductor chips stacked on the first semiconductor chips in a steplike shape along a second direction opposite the first direction, first pad wires electrically connecting first bonding pads of the first semiconductor chips with each other, second pad wires electrically connecting second bonding pads of the second semiconductor chips with each other, a first substrate wire electrically connecting the first substrate pad with a first bonding pad of any one among the first semiconductor chips except for a lowermost first semiconductor chip, and a second substrate wire electrically connecting the second substrate pad with a second bonding pad of any one among the second semiconductor chips except for a lowermost second semiconductor chip.

A dicing die attach film containing a dicing film and a die attach film stacked on the dicing film, wherein the die attach film contains an organic solvent having a boiling point of 100° C. or more and less than 150° C. and a vapor pressure of 50 mmHg or less, and wherein an amount of the organic solvent in the die attach film satisfies the following (a):

(a) when 1.0 g of the die attach film is immersed in 10.0 mL of acetone at 4° C. for 24 hours, an amount of the organic solvent extracted into the acetone is 800 μg or less.

A method of manufacturing a package which comprises encapsulating at least part of an electronic chip by an encapsulant, subsequently covering a part of the electronic chip with a chip attach medium, and attaching the encapsulated electronic chip on a chip carrier via the chip attach medium.

A substrate evaluation chip is used to perform a test for evaluating a thermal characteristic of a mounting substrate that is mountable a power semiconductor. The substrate evaluation chip includes an insulating substrate bonded with the mounting substrate, and a heating pattern that is formed on a surface of the insulating substrate by a metallic film and is arranged by having a predetermined shape that is optimized to beat the insulating substrate more uniformly. The insulating substrate is a substrate in which an insulating film is formed on a surface of a single crystal substrate having a thermal conductivity of 250 [W/mK] or more.

A terahertz element of an aspect of the present disclosure includes a semiconductor substrate, first and second conductive layers, and an active element. The first and second conductive layers are on the substrate and mutually insulated. The active element is on the substrate and electrically connected to the first and second conductive layers. The first conductive layer includes a first antenna part extending along a first direction, a first capacitor part offset from the active element in a second direction as viewed in a thickness direction of the substrate, and a first conductive part connected to the first capacitor part. The second direction is perpendicular to the thickness direction and first direction. The second conductive layer includes a second capacitor part, stacked over and insulated from the first capacitor part. The substrate includes a part exposed from the first and second capacitor parts. The first conductive part has a portion spaced apart from the first antenna part in the second direction with the exposed part therebetween as viewed in the thickness direction.

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.

To provide an electronic component in which the bonding position and bonding strength of a lead terminal can be maintained even if re-heated, a crystal oscillator as an electronic component includes: a first substrate having a connection terminal; and a lead terminal having a connection pad connected to the connection terminal of the first substrate via an electrically conductive bonding member. The electrically conductive bonding member has a part overlapping with the connection terminal and the connection pad, and a part arranged on the outside of the connection pad, as viewed in a plan view. The connection pad is provided with a first area overlapping with the connection terminal and a second area extending from the first area. The second area is connected to the first substrate via an insulative bonding member.