Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers with cavities formed into the top and/or bottom. The cavities may then be used as locations for the electronic components. Alternatively, narrow spacer interposers may be used to space apart standard more laterally elongated interposers to form the indentations used to house the electronic components. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products.

A memory card includes an upper case, a lower case, and an integrated circuit package between the upper case and the lower case. The integrated circuit package includes a memory stacked chip on a panel substrate, and the memory stacked chip includes a base memory stacked chip and an additional memory stacked chip stacked on the base memory stacked chip. The integrated circuit package includes a frequency boosting interface chip on the panel substrate and electrically connected to the memory stacked chip, and a controller chip on the panel substrate and electrically connected to the memory stacked chip and the frequency boosting interface chip.

Provided is a semiconductor device capable of suppressing misalignment of a brazing material when bonding a metal terminal to a metal circuit pattern. The semiconductor device includes an insulating substrate with a metal circuit pattern formed in a surface thereof and a metal terminal bonded onto the metal circuit pattern via a hard brazing material, in which protrusions are provided on the metal circuit pattern, and the protrusions are in contact with the hard brazing material.

A semiconductor device includes a support member, a first switching element, a second switching element, a first passive element, a second passive element, and an electrical conductor. The support member includes a plurality of wiring parts, and the plurality of wiring parts include a first wiring section and a second wiring section spaced apart from each other in a first direction perpendicular to the thickness direction of the support member. The first switching element is electrically connected to the first wiring section. The second switching element is electrically connected to the first switching element and the second wiring section. The first passive element has a first electrode and a second electrode, and the first electrode is bonded to the first wiring section. The second passive element has a third electrode and a fourth electrode, and the fourth electrode is bonded to the second wiring section. The electrical conductor connects the second electrode and the third electrode to each other. At least one of the first passive element and the second passive element is a capacitor.

A package structure is provided herein, which includes a substrate, an integrated transistor, and an encapsulation structure. The integrated transistor is disposed on the substrate and includes a transistor, a capacitor, a resistor, a first Zener diode, and a second Zener diode. The transistor includes a gate, a drain, and a source. The capacitor is electrically connected to the gate, and the resistor is electrically connected to the gate. The first Zener diode includes a first anode and a first cathode electrically connected to the gate. The second Zener diode includes a second anode electrically connected to the first anode and a second cathode electrically connected to the source. The encapsulation structure encapsulates the integrated transistor. The package structure includes a gate terminal, a drain terminal, and a source terminal.

A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.

A through electrode substrate includes: a substrate having a first surface and a second surface facing the first surface; through electrodes penetrating through the substrate; and a first capacitor including a first conductive layer, an insulating layer, and a second conductive layer, arranged on the first surface side of the substrate, and electrically connected with at least one of the through electrodes. The first conductive layer is arranged on the first surface side of the substrate and is electrically connected with the through electrode. The insulating layer includes a first part and a second part and is arranged on the first conductive layer. The second conductive layer is arranged on the insulating layer. The first part is arranged between the first conductive layer and the second conductive layer. The second part covers at least a part of a side surface of the first conductive layer.

A semiconductor device includes a substrate, a semiconductor chip, and a sealing member. The semiconductor chip is disposed on the substrate. The semiconductor chip includes a first principal surface on a side of the substrate and a second principal surface on a side opposite to the first principal surface. The sealing member seals the semiconductor chip. The sealing member includes a first sealing member and a second sealing member. The second sealing member faces at least a part of the second principal surface. A permittivity of the second sealing member is lower than a permittivity of the first sealing member.

An electronic device has a plurality of integrated circuits fixed to a support between transmitting and receiving antennas. An integrated circuit generates a synchronization signal supplied to the other integrated circuits. Each integrated circuit is formed in a die integrating electronic components and overlaid by a connection region according to the Flip-Chip Ball-Grid-array or embedded Wafer Level BGA. A plurality of solder balls for each integrated circuit is electrically coupled to the electronic components and bonded between the respective integrated circuit and the support. The solder balls are arranged in an array, aligned along a plurality of lines parallel to a direction, wherein the plurality of lines comprises an empty line along which no solder balls are present. A conductive synchronization path is formed on the support and extends along the empty line of at least one integrated circuit, between the solder balls of the latter.

A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.