Embodiments of the present disclosure are directed to organic spacers for integrated circuits. Among other things, the organic spacers of the embodiments of the present disclosure help provide a cost-efficient and effective solution to address issues such as coefficient of thermal expansion (CTE) mismatches, dynamic warpage, and solder joint reliability (SJR). Other embodiments may be described and claimed.

A protection device is provided for protecting an electrostatic discharge (ESD), sensitive device against an electromagnetic interference (EMI), event and/or an ESD event occurring on at least one of a first and second data line the ESD sensitive device is electrically connected to. Aspects of the present disclosure further relate to a system including an ESD sensitive device that is operatively coupled to a further device using a first and second data line, and the system includes the abovementioned protection device. The protection device uses a first inductor and/or second inductor and a first and/or shunt unit that each provide an electrical path between the first data line and/or second data line and ground in dependence of a voltage over the first and/or second inductor.

A semiconductor chip stack module that includes a substrate, two first semiconductor chips supported by the substrate, and a second semiconductor chip stacked on both of the two first semiconductor chips. The second semiconductor chip is electrically connected to both of the two first semiconductor chips by a conductive paste configured between the second semiconductor chip and both of the two first semiconductor chips. As multiple standard chips are stacked in the power module, and their number as well as the connection methods (e.g. series or parallel) are flexible so that the user can choose which electric characteristic(s) to be increased in the power module with the stacked chips.

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

A semiconductor device includes a semiconductor unit including a semiconductor chip, a cooling plate having a cooling front surface on which the semiconductor unit is disposed, a case disposed along an outer edge of the cooling front surface at the outer edge via an adhesive so as to surround the semiconductor unit, and a sealing member sealing the semiconductor unit disposed on the cooling plate inside the case. The cooling plate has an interlocking portion, the interlocking portion including a recess in the cooling front surface, and an engagement surface disposed inside the recess and being inclined at an acute angle with respect to the cooling front surface.

A semiconductor package according to the exemplary embodiments of the disclosure includes a base substrate including a base bonding pad, a first semiconductor chip disposed on the base substrate, a first adhesive layer provided under the first semiconductor chip, a first bonding pad provided in a bonding region on an upper surface of the first semiconductor chip, a first bonding wire interconnecting the base bonding pad and the first bonding pad, and a crack preventer provided in a first region at the upper surface of the first semiconductor chip. The crack preventer includes dummy pads provided at opposite sides of the first region and a dummy wire interconnecting the dummy pads.

A semiconductor device manufacturing method includes preparing a semiconductor chip and a conductive plate having a front surface that includes a disposition area on which the semiconductor chip is to be disposed, forming a supporting portion in a periphery of the disposition area of the conductive plate such that the supporting portion protrudes from a bottom of the disposition area in an upward direction orthogonal to the front surface of the conductive plate, bonding the semiconductor chip to the disposition area via bonding material applied to the disposition area, coating the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with a coating layer, and after the coating, sealing the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with sealing material.

A power semiconductor module includes an insulating substrate, conductor patterns and a power semiconductor element. The conductor patterns are formed on both surfaces of the insulating substrate. The power semiconductor element is mounted on the conductor patterns. The conductor patterns include an anode terminal connection portion and a cathode terminal connection portion. A circuit is formed such that a current that flows between the anode terminal connection portion and the cathode terminal connection portion via the power semiconductor element flows on the both surfaces of the insulating substrate.

A semiconductor apparatus includes: an insulating substrate including a circuit pattern; a semiconductor device mounted on the insulating substrate and electrically connected to the circuit pattern; a case storing the insulating substrate and the semiconductor device; and an electrode attached to the case, wherein a tip surface of the electrode is jointed to the circuit pattern with solder, the electrode is brought into contact with and pushed against the circuit pattern by the case, and a projection is provided on the tip surface.

A semiconductor device includes: a metal sheet; an insulating pattern provided on the metal sheet; a power circuit pattern and a signal circuit pattern that are provided on the insulating pattern; a power semiconductor chip mounted on the power circuit pattern; and a control semiconductor chip that is mounted on the signal circuit pattern and controls the power semiconductor chip. The power semiconductor chip is bonded to the power circuit pattern with a first die bonding material comprised of copper, and the control semiconductor chip is bonded to the signal circuit pattern with a second die bonding material.