A chip package structure can include: a lead frame having a carrier substrate and a first lead around the carrier substrate; a first conductive post arranged on the first lead and electrically coupled with the first lead; a first chip having an active face and an inactive face opposite to the active face and attached to the carrier substrate, and electrode pads on the active face are provided with a first electrical connector; a first plastic package configured to fully encapsulate the first chip, and to partly encapsulate the lead frame, where the first plastic package includes a first surface and a second surface opposite to the first surface, where the first conductive post and the first electrical connector are exposed on the first surface, and where the first lead is exposed on the second surface, and a second lead being arranged on the first surface.

A current breaker includes a semiconductor substrate in which a switching element is provided, a first electrode provided on a surface of the semiconductor substrate, a second electrode provided on the surface and separated from the first electrode, a resistive film provided on the surface and connecting the first electrode and the second electrode, a terminal, a bonding wire connecting the first electrode and the terminal, and a control element configured to turn on the switching element when a voltage between both ends of a current path including the resistive film exceeds a threshold value. The switching element is connected to at least one of the first electrode and the second electrode.

A semiconductor device includes a semiconductor element, a bonding wire that is electrically connected to the semiconductor element, a connection terminal, and sealing material that seals the semiconductor element, the bonding wire, and a part of the connection terminal. In addition, the connection terminal includes a plate-shaped lead part having a bonding area to which the bonding wire is bonded and an anchor part protruding from a first side part of the lead part. In the semiconductor device, since the rear surface of a die pad and the rear surface of the lead part exposed to the outside in a sealing main surface of the sealing material occupy a predetermined area or more, the heat dissipation of the semiconductor device is improved.

A semiconductor device according to an embodiment comprises a substrate, an epitaxial layer on the substrate, and a cluster including a plurality of particles disposed on the epitaxial layer, the particles being disposed to be apart from each other, and contacting the epitaxial layer.

Devices and methods are disclosed, related to shielding and packaging of radio-frequency (RF) devices on substrates. In some embodiments, A radio-frequency (RF) module comprises a lead-frame package with a plurality of pins and at least one pin exposed from overmold compound. The module further includes a metal-based covering over a portion of the lead-frame package. Additionally, the metal-based covering can be in contact with the at least one pin.

The disclosure relates to an integrated circuit and associated method and packaged integrated circuit. The integrated circuit comprises a first pad; a second pad; an active element having a node that is capacitively coupled to the first and second pads; a voltage or current source connected to the first pad; and a detection module connected to the second pad and configured to determine an electrical continuity between the second pad and the first pad.

A semiconductor device has a first semiconductor die stacked over a second semiconductor die which is mounted to a temporary carrier. A plurality of bumps is formed over an active surface of the first semiconductor die around a perimeter of the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. A plurality of conductive vias is formed through the encapsulant around the first and second semiconductor die. A portion of the encapsulant and a portion of a back surface of the first and second semiconductor die is removed. An interconnect structure is formed over the encapsulant and the back surface of the first or second semiconductor die. The interconnect structure is electrically connected to the conductive vias. The carrier is removed. A heat sink or shielding layer can be formed over the encapsulant and first semiconductor die.

A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

A semiconductor package includes a semiconductor die including a semiconductor substrate, a strain-sensitive component located within or over a metallization layer of the semiconductor die, wherein a parameter of the strain-sensitive component exhibits a longitudinal shift due to a longitudinal strain and a transverse shift due to a transverse strain, and a mold compound covering the semiconductor die and the strain-sensitive component. The semiconductor package, including the semiconductor die and the mold compound, defines an orthogonal package-induced strain ratio on the strain-sensitive component on the semiconductor die surface. The strain-sensitive component is located such that the longitudinal shift due to package-induced strains offsets the transverse shift due to the package-induced strains.

An electronic package device and a carrier structure thereof are provided. The carrier structure includes a die attach paddle, a ground frame, a pin assembly, and a ground wing portion. The ground frame surrounds the die attach paddle. The pin assembly includes a plurality of pins that are spaced apart from one another. The pins extend radially outward and are arranged to surround the ground frame. The ground wing portion is connected to the ground frame and located in a space under the pin assembly. The ground wing portion includes an extending part and a joint part, the extending part extends away from the die attach paddle, and a top end of the extending part is located at a position above where a bottom surface of the die attach paddle is located.