Implementations of a semiconductor package system may include a first bond wire bonded to a portion of a leadframe and to a pad of a semiconductor die, the first bond wire coupled to one of a power source or a ground; and a second bond wire bonded to the portion of the leadframe and to a control integrated circuit. The portion of the leadframe may form a current sense area and the control integrated circuit may be configured to use the second bond wire and the current sense area to measure a current flowing through the first bond wire during operation.

A semiconductor module includes: a supporting substrate; a conductive substrate bonded to the supporting substrate; a switching semiconductor element electrically bonded to the conductive substrate; and a conducting member that forms a path of a main circuit current switched by the semiconductor element. The conducting member is arranged to overlap with the obverse surface of the conductive substrate as viewed in a thickness direction of the supporting substrate. The conducting member is formed with an opening that overlaps with the obverse surface of the conductive substrate and does not overlap with the semiconductor element as viewed in the thickness direction.

An integrated circuit package includes a semiconductor die having a first surface and a second surface. The first surface is attached to a top surface of a die attach pad, and the second surface has a sensing area thereon. A mold compound covers or encapsulates at least a portion of the die attach pad and the semiconductor die. A channel is formed in a top portion of the mold compound. The channel extends from a first side of the mold compound to a second side of the mold compound. A cavity is formed between the channel and the sensing area so that the sensing area is exposed to the environment.

A light emitting device includes: a base comprising a first lead, a second lead, and a supporting member; a light emitting element mounted on the first lead; a protection element mounted on the second lead; a wire including a first end and a second end, wherein the first end is connected to an upper surface of the first lead, and the second end is connected to a first terminal electrode of the protection element; a resin frame located on an upper surface of the base, wherein the resin frame covers at least part of the protection element and surrounds the light emitting element and the first end of the wire; a first resin member surrounded by the resin frame and covering the light emitting element and the first end of the wire; and a second resin member covering the resin frame and the first resin member.

Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

A semiconductor device including a die pad, a semiconductor element, a first joining layer, a first conductive member, and a second joining layer. The die pad has an obverse surface facing in a thickness direction. The semiconductor element has a first electrode provided opposing the obverse surface, and a second electrode provided on the opposite side to the first electrode in the thickness direction. The first electrode is electrically joined to the obverse surface. The first joining layer electrically joins the first electrode and the obverse surface to each other. The first conductive member is electrically joined to the second electrode. The second joining layer electrically joins the first conductive member and the second electrode to each other. The melting point of the first joining layer is higher than the melting point of the second joining layer.

A palladium-coated copper bonding wire includes: a core material containing copper as a main component; and a palladium layer on the core material, in which a concentration of palladium relative to the entire wire is 1.0 mass % or more and 4.0 mass % or less, and a work hardening coefficient in an amount of change of an elongation rate 2% or more and a maximum elongation rate εmax % or less of the wire, is 0.20 or less.

A lead frame includes a plurality of lead frame units. An upper surface of each of the plurality of lead frame units includes a soldering region and a non-soldering region outside of the soldering region. The non-soldering region includes a rough surface, and the soldering surface includes no rough surface. Each of the plurality of lead frame units may include a base island and a plurality of pins arranged around the base island, and the soldering region may be arranged on the base island and/or on the plurality of pins. The soldering region my include a wire-bonding soldering portion that connects to a chip via a bonding wire. Each of the plurality of lead frame units may include a plurality of pins, and the soldering region and the non-soldering region are arranged on the plurality of pins.

Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.