A package for integrated circuits includes a base substrate having a mounting face. A first electronic chip has a top face electrically connected to the mounting face and a bottom face mounted to the mounting face by an adhesive layer. A second electronic chip has a bottom face covered with a thermal interface layer and a top face electrically connected to the mounting face. A heat sink includes a first part embedded in the adhesive layer, a second part having a bottom face in contact with the layer of thermal interface material and a top face, and a connection part between the first part and the second part. A coating encapsulates the first and second electronic chips and the heat sink. The top face of the second part of the heat sink exposed from the encapsulating coating.

A semiconductor package comprises an encapsulation having a first lateral side and an opposite second lateral side, at least one power semiconductor chip having a drain contact region running along the first lateral side, a source contact region running along the second lateral side, and first and second inner contact regions arranged between the drain and source contact regions, a first external terminal which is connected to the drain contact region, is arranged centrally on the first lateral side, and is configured to apply a supply voltage for the at least one power semiconductor chip, a second external terminal which is connected to the source contact region, is arranged centrally on the second lateral side, and is configured to apply a reference voltage for the at least one power semiconductor chip, third and fourth external terminals which are connected to the first inner contact region. are arranged opposite each other at a first end of the first and second lateral sides, respectively, and are configured a first output of the semiconductor package, and fifth and sixth external terminals which are connected to the second inner contact region and are arranged opposite each other at a second end of the first and second lateral sides, respectively, and are configured as a second output of the semiconductor package.

A semiconductor package includes a lead frame that includes a die pad and a plurality of leads, a semiconductor die mounted on a die attach surface of the die pad, an encapsulant body of electrically insulating material that covers semiconductor die and portions of the lead frame, and a fastener receptacle that includes a blind hole in the encapsulant body or the die pad, wherein a rear surface of the die pad is exposed from a first main face of the encapsulant body.

A semiconductor package includes: a semiconductor device; a lead frame; a built-in package including an insulated driver having a multi-chip configuration and driving the semiconductor device; a wire connecting the built-in package to the semiconductor device; and a resin sealing the semiconductor device, the lead frame, the built-in package, and the wire, wherein the built-in package is directly joined to the lead frame.

Provided is an electric circuit body including: a power semiconductor element; a first conductor plate configured to be connected to one surface of the power semiconductor element; a first sheet-shaped member having a first resin insulation layer and configured to at least cover a surface of the first conductor plate; a sealing material configured to seal each of the power semiconductor element, the first conductor plate, and an end of the first sheet-shaped member; and a first cooling member configured to be adhesively attached to the first sheet-shaped member. In the electric circuit body, the first sheet-shaped member includes : an embedded portion where the end of the first sheet-shaped member is covered with the sealing material; a heat dissipation surface as a region to overlap the surface of the first conductor plate; and a margin as a region between the embedded portion and the heat dissipation surface, the margin is located more inward than the heat dissipation surface, and the embedded portion is located more inward than the margin.

There is disclosed a packaged semiconductor device comprising: a leadframe having a first thickness; the leadframe comprising a die pad; a semiconductor die thereabove; and epoxy therebetween and arranged to bond the semiconductor die to the die pad; wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness; wherein the die pad has at least one through-hole in the at least one region; and wherein the epoxy fills the at least one through-hole and extends thereunder and laterally beyond the through-hole. Corresponding leadframes, and an associated method of manufacture are also disclosed.

A semiconductor device having a fan-out package structure includes a semiconductor element having a first electrode pad and a second electrode pad on a front surface, a sealing material covering a side surface of the semiconductor element and a redistribution layer covering the front surface of the semiconductor element and a part of the sealing material. The redistribution layer includes an insulation layer, a first redistribution wire and a second redistribution wire. At least a part of the first redistribution layer is disposed above a boundary between the side surface of the semiconductor element and the sealing material. The second redistribution wire is electrically connected to the second electrode pad, and at least has a part that extends to a position outside of a contour of the semiconductor element over the first redistribution wire. The second redistribution wire is electrically independent of the first redistribution wire.

The third side surface includes inclined surfaces inclined in a direction in which a center in an up-down direction of the third side surface is convex. The mold resin further includes a residual section provided in the center of the third side surface and a dowel section provided between the inclined surface and the residual section. The dowel section projects further in a lateral direction than the inclined surface. The residual section further projects in the lateral direction than the dowel section and has a fracture surface perpendicular to the up-down direction.

One example described herein includes a method for fabricating integrated circuit (IC) packages. The method includes fabricating a plurality of IC dies and providing a conductive metal material sheet. The method also includes laser-cutting the conductive metal material sheet to form a lead-frame sheet. The lead-frame sheet includes at least one of through-holes and three-dimensional locking features. The method further includes coupling the IC dies to the lead-frame sheet and coupling the lead-frame sheet and the IC dies to packaging material to form an IC package block comprising the IC packages.

According to a first aspect of the present invention there is provided a quad-flat-no-leads (QFN) packaged semiconductor device having a QFN bottom surface and QFN side faces, wherein the QFN side faces each comprise an upper portion and a recessed lower portion, the QFN packaged semiconductor device comprising: a die pad within or on the QFN bottom surface; a plurality of I/O terminals spaced apart from the die pad and around a periphery of the bottom surface, each having a bottom face extending from an inner end to a peripheral end, an exposed side face on a QFN side face and extending above the recessed lower portion of the QFN side face; wherein the QFN bottom surface includes at least one trench therein, parallel to a one of the QFN side faces and exposing at least a part of a side face of the inner end of the I/O terminals. The trench may provide for additional surface area, and provide a stronger solder joint when the QFN packaged semiconductor device is soldered to a substrate or circuit board.