A signal transmission device comprises: a first lead frame having a first major surface and a second major surface opposite to the first major surface; a second lead frame having a third major surface and a fourth major surface and isolated from the first lead frame, the fourth major surface located opposite to the third major surface; a transmission circuit that sends a transmission signal, the transmission circuit located on the first major surface of the first lead frame; a receiving circuit located on the third major surface of the second lead frame; and an electromagnetic resonance coupler located across between the second major surface of the first lead frame and the fourth major surface of the second lead frame to transmit the transmission signal, sent by the transmission circuit, to the receiving circuit in a contactless manner.

A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet. A side of the supporting sheet away from the conductive surface is fixed to the cavity of the shell.

A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.

A converter includes a plurality of active circuitry elements over a substrate. The converter further includes a passivation structure over the plurality of active circuitry elements, the passivation structure having at least one opening that is configured to expose at least one electrical pad of each active circuitry element. The converter further includes a plurality of passive electrical components over the passivation structure, wherein each passive electrical component is selectively connectable with at least one other passive electrical component, and a first side of each passive electrical component is electrically coupled to an electrical pad of each of at least two active circuitry elements. The converter further includes a plurality of electrical connection structures, wherein a first electrical connection structure electrically couples an electrical pad of a first active circuitry element to a corresponding passive electrical component, and the first electrical connection structure is completely within the passivation structure.

A packaged RF amplifier device includes a transistor and an output circuit. The transistor includes a control terminal and first and second current carrying terminals. The output circuit is coupled between the first current carrying terminal and an output lead. The output circuit includes first and second inductive elements coupled in series. The first inductive element, which may be a first bondwire array or an integrated inductance, is coupled between the first current carrying terminal and a node. The second inductive element, which includes a second bondwire array, is coupled between the node and the output lead. The device also includes a shunt circuit with a shunt capacitor and a third bondwire array coupled between the first current carrying terminal and the shunt capacitor. The first and second inductive elements and the third bondwire array are configured to have a desired mutual inductance.

A converter includes a plurality of active circuitry elements over a substrate. The converter further includes a passivation structure over the plurality of active circuitry elements, the passivation structure having at least one opening that is configured to expose at least one electrical pad of each active circuitry element. The converter further includes a plurality of passive electrical components over the passivation structure, wherein each passive electrical component is selectively connectable with at least one other passive electrical component, and a first side of each passive electrical component is electrically coupled to an electrical pad of each of at least two active circuitry elements. The converter further includes a plurality of electrical connection structures, wherein a first electrical connection structure electrically couples an electrical pad of a first active circuitry element to a corresponding passive electrical component, and the first electrical connection structure is completely within the passivation structure.

A semiconductor device includes a conductive base, a first chip and a second chip that are mounted on the base, and a first bonding wire that electrically connects the first chip to the second chip and transmits a high frequency signal. The base has a first opening extending through the base in a thickness direction of the base and overlapping at least a part of the first bonding wire with no conductor layer interposed between the first opening and the at least a part of the first bonding wire as viewed in the thickness direction of the base.

A disclosed circuit arrangement includes a substrate, an integrated circuit (IC) component attached to the substrate, first and second cross wires attached to the substrate and disposed proximate the electronic device, and one or more wire segments attached to the substrate. The one or more wire segments have first and second portions attached at a third portion of the first cross wire and at a fourth portion of the second cross wire, respectively. The first and second cross wires and the one or more wire segments are round wires having round cross sections. The first portion and the third portion have flat areas of contact, and the second and fourth portions have flat areas of contact. A first bond wire is connected to the electronic device and to the first portion of the one or more wire segments, and a second bond wire is connected to the electronic device and to the second portion of the one or more wire segments.

An integrated circuit (IC) package and assembly includes a stacked arrangement of one or more IC die to leverage additional functionality in a standard package width. Active IC die and high voltage IC capacitors may be stacked in various arrangements to minimize the footprint and width of the IC package. The die are interconnected with each other and a lead frame with wire bonds, silicon vias or other interconnections. Various bond pad configurations are used to interconnect the die. The stacked arrangement of the IC die reduces the width of the supporting lead frame and reduces the overall footprint of the IC package.

According to one embodiment, a semiconductor device c includes: a package substrate including a base including a mount portion, and terminals; a semiconductor chip including a first pad to which a ground voltage is supplied, a second pad electrically connected to a first terminal among the terminals, and a semiconductor circuit connected to the first and second pads, the semiconductor chip being provided above the mount portion; and a first capacitor chip including a first capacitor unit provided in a silicon substrate, a first node supplied with the ground voltage, and a second node electrically connected to the second pad, the first capacitor chip being provided above the mount portion.