A wire bonding method comprises: preparing a wire bonding apparatus; a step of forming a free air ball; a first height measuring step of measuring the height of a first electrode by detecting whether the free air ball is grounded to the first electrode; a second height measuring step of measuring the height of a second electrode by detecting whether the free air ball is grounded to the second electrode; a first bonding step of controlling the height of a bonding tool based on the measurement result in the first height measuring step, and bonding the free air ball to the first electrode; and a second bonding step of controlling the height of the bonding tool based on the measurement result in the second height measuring step, and bonding a wire to the second electrode to connect the first and the second electrodes. Thus, electrodes can be correctly bonded.

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including -alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

A semiconductor element includes an insulation layer and a pad portion for electrical connection to an external portion by wire bonding. The insulation layer includes a plurality of projections projecting from a main surface of the insulation layer. The pad portion is disposed on an upper surface of each of the projections without extending beyond the upper surface of the projection on which the pad portion is formed.

An inertial sensor according to the present disclosure includes a sensor element having a multilayer structure in which a first substrate, a second substrate, and a sensor substrate are stacked one on top of another. The first substrate includes a substrate body, a first interconnect, an electrode layer, and a silicon member. The first interconnect is provided inside the substrate body. The electrode layer is provided for the substrate body and electrically connected to the first interconnect. The silicon member is provided at an end of the substrate body. The silicon member has, in a cross-sectional view, a curved portion and a linear portion connected to the curved portion. The electrode layer is provided to cover the curved portion and the linear portion.

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.

An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit is formed including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit. A pad conductive layer is formed that at least partially includes a pad for connecting to a circuit outside the substrate. An insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view and is connected to a ground (GND) potential connected to the amplifier circuit.