Semiconductor device A1 of the present disclosure includes: semiconductor element 10 (semiconductor elements 10A and 10B) having element obverse face and element reverse face facing toward opposite sides in z direction; support substrate 20 supporting semiconductor element 10; conductive block 60 (first block 61 and second block 62) bonded to element obverse face via first conductive bonding material (block bonding materials 610 and 620); and metal member (lead member 40 and input terminal 32) electrically connected to semiconductor element 10 via conductive block 60. Conductive block 60 has a thermal expansion coefficient smaller than that of metal member. Conductive block 60 and metal member are bonded to each other by a weld portion (weld portions M4 and M2) at which a portion of conductive block 60 and a portion of metal member are welded to each other. Thus, the thermal cycle resistance can be improved.

Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.

A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

A silicon carbide semiconductor device includes a metal plate having a first main surface and a second main surface, the second main surface being opposite to the first main surface, an insulating film provided on a portion of the first main surface of the metal plate, a first conductive layer provided on the insulating film, and a silicon carbide semiconductor chip. The silicon carbide semiconductor chip includes a first electrode and a second electrode on a first surface and a third electrode on a second surface, the second surface being opposite to the first surface. The first surface of the silicon carbide semiconductor chip faces the first main surface of the metal plate, the first electrode is bonded to the first conductive layer with a first bonding material, and the second electrode is bonded to the first main surface of the metal plate with a second bonding material.

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

A power electronics module includes a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module; a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer; a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode.

The carrier-foil-attached ultra-thin copper foil according to one embodiment of the present invention comprises a carrier foil, a release layer, a first ultra-thin copper foil, an Al layer, and a second ultra-thin copper foil, wherein the release layer may comprise a first metal (A1) having peeling properties, and a second metal (B1) and third metal (C1) facilitating the plating of the first metal (A1).

In one embodiment, a power semiconductor module includes a main substrate, semiconductor chips mounted on the main substrate, and an auxiliary substrate also mounted on the main substrate. The power semiconductor module is capable of handling a current of 10 A or more. The auxiliary substrate is a printed circuit board having at least one carrier layer that is based on an organic material. The auxiliary substrate provides a common contact platform for at least some of the first semiconductor chips. The auxiliary substrate is attached to the main substrate by a joining layer located at a bottom side of the at least one auxiliary substrate facing the main substrate. The joining layer is a continuous organic adhesive layer of an adhesive foil or a double-faced adhesive tape.