A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the second insulating plate and the second semiconductor chip, a third bonding material provided between the second metal plate and the second semiconductor chip, the third bonding material bonding the second metal plate and the second semiconductor chip, a fourth bonding material provided between the second base material and the second insulating plate, the fourth bonding material bonding the second base material and the second insulating plate, and a first base bonding portion provided between the second side surface and the first side surface and bonded to the first side surface and the second side surface.

Implementations of a semiconductor package may include a semiconductor die including a first side and a second side where the first side of the semiconductor die includes one or more electrical contacts; a layer of metal coupled to the second side of the semiconductor; and a stress balance structure coupled to one of the layer of metal or around the one or more electrical contacts.

When a distance between an end portion of a brazing material and a downward extended line of a side surface of an insulating substrate is taken as a, and a distance between an end portion of a solder resist on the side of a solder and the downward extended line of the side surface of the insulating substrate is taken as b, the positional relationship a<b is satisfied. The position of the end portion of the solder is regulated by the solder resist, and the position of the end portion of the brazing material on the side of the side surface of the insulating substrate is closer to the side of the side surface of the insulating substrate than to the position of the end portion of the solder on the side of the side surface of the insulating substrate.

A electronic device includes a substrate, a first metal film, an insulating film, a second metal film, and a third metal film. The substrate has one surface. The first metal film is disposed on the one surface. The insulating film is disposed on the one surface in a state covering the first metal film. The insulating film has a contact hole exposing the first metal film. The second metal film is disposed on a portion of the first metal film exposed from the contact hole and a periphery of the contact hole. The third metal film is made of gold and disposed on the second metal film. The first metal film, the second metal film, and the third metal film are stacked as a pad portion.

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.