A redistribution assembly may have multiple layers. Each layer may include a signal conductor and a ground conductor. The width of the ground conductors may exceed the width of the signal conductors. In addition, the layers may be vertically positioned over each other to form the redistribution layer assembly. The conductors may be interleaved such that the ground conductor of a top layer is vertically positioned over the signal conductor for a bottom layer and the signal conductor of the top layer is positioned over the ground conductor of the bottom layer. Multi-layer redistribution layer assemblies may be used with stacks of dies in an IC package to create a fly-by topology that provides electrical continuity in the X, Y and Z dimensions.

Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.

A semiconductor chip package is provided with improved connections between different components within the package. The semiconductor chip package may comprise a semiconductor chip disposed on a substrate. The semiconductor chip may have a first surface and a second surface. The first surface of the semiconductor chip may be connected to the substrate. The semiconductor chip package may comprise a leadframe that includes a first lead and a second lead. The first lead of the leadframe may be directly attached to the second surface of the semiconductor chip. The second lead of the leadframe may be directly attached to the substrate.

For communication across a capacitively coupled channel, an example circuit includes a first plate substantially parallel to a substrate, forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

In one embodiment, a semiconductor device includes a substrate, and a first shield member provided on or in the substrate. The device further includes a semiconductor chip provided on the first shield member, and a first wire electrically connected to the semiconductor chip and the substrate. The device further includes a second wire electrically or magnetically connected to the first shield member, and a second shield member provided above the semiconductor chip, electrically insulated from the first wire, and electrically or magnetically connected to the second wire.

An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce V.sub.CE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.

A semiconductor arrangement includes a controllable semiconductor element having an active region, and bonding wires arranged in parallel to each other in a first horizontal direction. The active region has a first length in the first horizontal direction and a first width in a second horizontal direction perpendicular to the first horizontal direction. Each bonding wire is electrically and mechanically coupled to the controllable semiconductor element by a first number of bond connections arranged above the active region. A first bond connection of each bonding wire is arranged at a first distance from a first edge of the active region. A second bond connection of each bonding wire is arranged at a second distance from a second edge of the active region opposite the first edge. The first and second distances are both less than the first length divided by twice the first number of bond connections.

A buffer chip is wire-bonded to memory dies. A semiconductor package includes a semiconductor die stack, a first set of wire bonds connected to a first set of semiconductor dies, a second set of wire bonds connected to a second set of semiconductor dies, and the buffer chip. The second set of semiconductor dies are on the first set of semiconductor dies. The buffer chip includes a first set of die bond pads being close to the semiconductor die stack, and a second set of die bond pads being distant from the semiconductor die stack. The second set of wire bonds extends to the first set of die bond pads of the buffer chip, and the first set of wire bonds extends to the second set of die bond pads of the buffer chip.

Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

Devices including a transistor having a parasitic capacitance between a control terminal and a load terminal of a first type are provided. Furthermore, the devices include advantageously arranged inductances which are electromagnetically coupled to one another and are configured at least partly to compensate for an effect of the parasitic capacitance in a range around a resonant frequency.