A semiconductor package includes a package substrate, semiconductor chips stacked on the package substrate, and electrical connectors that connect internal circuitry of each of the chips to the package substrate. Each of the semiconductor chips includes a chip selection pad for transmitting a chip selection signal to the internal circuitry of the semiconductor chip and a chip dummy pad, electrically isolated from the internal circuitry, along a first side of the semiconductor chip. The electrical connectors include a lower chip connector that electrically connects the package substrate to the chip selection pad of the lower semiconductor chip, a first auxiliary connector that electrically connects the package substrate to the chip dummy pad of the lower semiconductor chip, and a second auxiliary connector that electrically connects the chip dummy pad of the lower semiconductor chip to the chip selection pad of the upper semiconductor chip.

An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce V.sub.CE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.

The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.

Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in this respect. Wire bonding methods can include providing a wire payout at a first location from a rolled wire source via a dispensation head, contacting a first metal nanoparticle composition and a first portion of the wire payout with a bonding pad, and at least partially fusing metal nanoparticles in the first metal nanoparticle composition together to form an adhering interface between the bonding pad and the first portion of the wire payout. The adhering interface can have a nanoparticulate morphology. Wire bonding systems can include a rolled wire source, a dispensation head configured to provide a wire payout, and an applicator configured to place a metal nanoparticle composition upon at least a portion of the wire payout or upon a bonding pad.

In one embodiment, a semiconductor device includes a substrate, and a first shield member provided on or in the substrate. The device further includes a semiconductor chip provided on the first shield member, and a first wire electrically connected to the semiconductor chip and the substrate. The device further includes a second wire electrically or magnetically connected to the first shield member, and a second shield member provided above the semiconductor chip, electrically insulated from the first wire, and electrically or magnetically connected to the second wire.

An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce V.sub.CE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.

Wire bonding operations can be facilitated through the use of metal nanoparticle compositions. Both ball bonding and wedge bonding processes can be enhanced in this respect. Wire bonding methods can include providing a wire payout at a first location from a rolled wire source via a dispensation head, contacting a first metal nanoparticle composition and a first portion of the wire payout with a bonding pad, and at least partially fusing metal nanoparticles in the first metal nanoparticle composition together to form an adhering interface between the bonding pad and the first portion of the wire payout. The adhering interface can have a nanoparticulate morphology. Wire bonding systems can include a rolled wire source, a dispensation head configured to provide a wire payout, and an applicator configured to place a metal nanoparticle composition upon at least a portion of the wire payout or upon a bonding pad.

A semiconductor package is disclosed including a number of stacked semiconductor die, electrically connected to each other with wire bonds. The stacked semiconductor die are provided in a mold compound such that a spacing exists between a top die in the die stack and a surface of the mold compound. The wire bonds to the top die may be provided in the spacing. An RDL pad is affixed to the surface of the mold compound. Columns of bumps may be formed on the die bond pads of the top die in the die stack to electrically couple the RDL pad to the die stack across the spacing.

An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.

An amplifier includes a package, a transistor chip having a gate pad and a drain pad formed elongately, the transistor chip being provided in the package, and a plurality of drain bonding wires connected to the drain pad, wherein the plurality of drain bonding wires include a first outer-most bonding wire connected to one of two end portions of the drain pad, a second outer-most bonding wire connected to the other of the two end portions of the drain pad, and an intermediate bonding wire interposed between the first outer-most bonding wire and the second outer-most bonding wire, each of the plurality of drain bonding wires is longer than 1 mm, and the first outer-most bonding wire and the second outer-most bonding wire have loop heights larger than a loop height that the intermediate bonding wire has.