It is an object of the present invention to provide a semiconductor device which allows an increase in the number of semiconductor elements mounted in parallel and prevents a shape of an insulating substrate onto which the semiconductor elements are mounted, from being laterally long, and provide a semiconductor module including such semiconductor device. A semiconductor device according to the present invention includes an insulating substrate, a metal pattern which is a continuous piece and is bonded to one main surface of the insulating substrate, and a plurality of switching elements which are bonded to a surface opposite to the insulating substrate on the metal pattern, and the plurality of switching elements are arranged in a matrix of two or more rows and two or more columns on the metal pattern.

Provided is a semiconductor device comprising; a semiconductor chip, a first electrode pair, a first wire group that has a plurality of bonding wires connecting electrodes of the first electrode pair in parallel, and a sealing portion that mold-seals said elements, wherein the plurality of bonding wires belonging to the first wire group are wired such that length of each of the bonding wires on a far side in a first direction parallel with an in-plane direction of the semiconductor chip is longer than length of each of the bonding wires on a near side, and each height at respective positions of each of the bonding wires on the far side in the first direction is not lower than each height at respective positions, corresponding to the respective positions of each of the bonding wires on the far side, of each of the bonding wires on the near side.

A semiconductor module includes a base plate, a substrate on the base plate and carrying at least one semiconductor chip, a housing attached to the base plate and at least partially enclosing the substrate, and at least one terminal having one end which protrudes from the housing and another end which has a terminal foot attached on a terminal pad of the metallization by means of ultrasonic welding. The housing has a protective wall which encloses the terminal and divides an interior space of the housing into an unprotected region and a protected region. The protective wall is formed such that a gap is formed between the substrate and the protective wall. The gap is designed to carry a fluid flow such that particles produced during the ultrasonic welding of the terminal foot to the terminal pad are prevented from penetrating into the protected region from the unprotected region.

A semiconductor module includes a base plate, a substrate on the base plate and carrying at least one semiconductor chip, a housing attached to the base plate and at least partially enclosing the substrate, and at least one terminal having one end which protrudes from the housing and another end which has a terminal foot attached on a terminal pad of the metallization by means of ultrasonic welding. The housing has a protective wall which encloses the terminal and divides an interior space of the housing into an unprotected region and a protected region. The protective wall is formed such that a gap is formed between the substrate and the protective wall. The gap is designed to carry a fluid flow such that particles produced during the ultrasonic welding of the terminal foot to the terminal pad are prevented from penetrating into the protected region from the unprotected region.

In a power semiconductor device, a front-surface electrode of a power semiconductor element is formed in such a manner that, on a first Cu layer consisting mainly of Cu, formed by non-electrolytic plating and having a Vickers hardness of 200 to 350 Hv, a second Cu layer consisting mainly of Cu, formed by non-electrolytic plating and having a Vickers hardness of 70 to 150 Hv and thus being softer than the first Cu layer, is laminated. The second Cu layer and a wire made of Cu are wire-bonded together.

Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.

Provided is a semiconductor package including a chip stack that includes first and second semiconductor chips stacked in a first direction and offset in a second direction intersecting the first direction, each of the first and second semiconductor chips comprising chip pads in the second direction, a redistribution substrate on the chip stack, first bonding wires connecting the redistribution substrate and the chip pads of the first semiconductor chip, and first vertical wires connecting the redistribution substrate and the chip pads of the second semiconductor chip. Each of the first bonding wires includes a first portion in contact with one of the chip pads of the first semiconductor chip and having a first width, and a second portion extending perpendicularly on the first portion and having a second width, each of the first vertical wires has a third width, and each of the second and third widths is smaller than the first width.