A semiconductor device includes a pair of spacers disposed on the surface of a substrate, the spacers are a first height and spaced from each other at a first distance along a first direction. A first semiconductor chip is mounted on the substrate surface. The first semiconductor chip has a second height that is less than the first height. The first semiconductor chip can be connected to the substrate with bonding wires or the like. A second semiconductor chip is mounted on the spacers and spans the distance between the spacers. The second semiconductor chip is above at least a portion of the first semiconductor chip. A projecting section is provided on the surface of the substrate between the spacers in the first direction. The projecting section is between the first semiconductor chip and an outer edge of the substrate and protrudes upward from the surface of the substrate.

A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a padding layer disposed on the substrate, a plurality of wires, a support, and a light-permeable layer disposed on the support. A top side of the padding layer is coplanar with a top surface of the sensor chip, the support is disposed on the top side of the padding layer and the top surface of the sensor chip, and the wires are embedded in the support. Terminals at one end of the wires are connected to the top surface of the sensor chip, and terminals at the other end of the wires are connected to the top side of the padding layer, so that the sensor chip can be electrically coupled to the substrate through the wires and the padding layer.

A semiconductor device includes a first electrode on a semiconductor element at a first location and a second electrode on the semiconductor element at a second location spaced from the first location. And insulating film covers the first electrode, the second electrode and a third electrode. First and second pads are on the insulating film. The first electrode contacts the first pad through an opening in a first portion of the insulating film. The second electrode contacts the second pad each through an opening in a second portion of the insulating film. A bonding surface of the first pad is at a first distance above one portion of the insulating film, and a second distance above another. A bonding surface of the second pad likewise at different distances above the insulating film depending on location.

A semiconductor package includes a substrate having thereon a high-frequency chip and a circuit component susceptible to high-frequency signal interference; a ground pad on the and between the high-frequency chip and the circuit component; a metal-post reinforced glue wall on the ground pad; a molding compound surrounding the metal-post reinforced glue wall and surrounding the high-frequency chip and the circuit component; and a conductive layer disposed on the molding compound and in contact with the metal-post reinforced glue wall. The metal-post reinforced glue wall comprises first metal posts and glue attached to the first metal posts. An interface between a base of each of the first metal posts and the ground pad has a root mean square (RMS) roughness that is less than 1.0 micrometer.

The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

The present disclosure provides a semiconductor package. The semiconductor package includes a carrier member, a plurality of inductors and a memory chip. The carrier member includes a first surface, a second surface and a centrally-located opening. The carrier member also includes a plurality of conductive pads on the second surface proximal to the opening. The memory chip is attached to the carrier member in a face-down manner. The memory chip includes a plurality of bidirectional and unidirectional signal-transmission pins electrically coupled to the inductors. The memory chip also includes a plurality of bonding pads. A plurality of bonding wires, passing through the opening, electrically connect the bonding pads on the memory chip to the conductive pads on the carrier member. A first insulative structure substantially encapsulates the memory chip and the inductors. A plurality of solder balls are attached to the second surface of the carrier member.

A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.

A microelectronic package may include a substrate having first and second surfaces each extending in first and second directions, a NAND wafer having a memory storage array, a bitline driver chiplet configured to function as a bitline driver, and a wordline driver chiplet configured to function as a wordline driver. The NAND wafer may be coupled to the first surface of the substrate, and the bitline and wordline driver chiplets may each be mounted to a front surface of the NAND wafer. The NAND wafer may have element contacts electrically connected with conductive structure of the substrate. The bitline and wordline driver chiplets may be elongated along the first and second directions, respectively. Front surfaces of the bitline driver chiplet and the wordline driver chiplet may be arranged in a single common plane and may be entirely contained within an outer periphery of the front surface of the NAND wafer.

The invention discloses a parallel electrode combination, which includes a first power module electrode and a second power module electrode, wherein a soldering portion of the first power module electrode and a soldering portion of the second power module electrode are respectively used to connect a copper layer of a power source inside a power module, and a connecting portion of the first power module electrode and a connecting portion of the second power module electrode are opposite in parallel. The invention further discloses a power module and a power module group using the parallel electrode combination. In the invention, the connecting portion of the first power module electrode and the connecting portion of the second power module electrode are opposite in parallel.