A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.

An example embodiment relates to a radiofrequency (RF) power amplifier pallet, and further relates to an electronic device that includes such a pallet. The RF power amplifier pallet may include a coupled line coupler that includes a first line segment and a second line segment that is electromagnetically coupled to the first line segment. A first end of the first line segment may be electrically connected to an output of an RF amplifying unit. The RF power amplifier pallet may further include a dielectric filled waveguide having an end section of the first dielectric substrate, an end section of the second dielectric substrate, and a plurality of metal wall segments covering the end sections of the first and second dielectric layers. The plurality of metal wall segments may be arranged spaced apart from the first line segment and electrically connected to a first end of the second line segment.

A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack.

In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure at least partially surrounding the chip including a multilayer stack. The multilayer stack includes a magnetic layer and a dielectric layer. A first magnetic region is located inside an inner surface of the magnetic field shielding structure and a second magnetic region is located immediately outside an outer surface of the magnetic field shielding structure. A magnetic field in the first magnetic region is less than a magnetic field in the second magnetic region.

Various embodiments relate to a packaged radio frequency (RF) amplifier device implementing a split bondwire where the direct ground connection of an output capacitor is replaced with a set of bondwires connecting to ground in a direction opposite to the wires connecting to the output of a transistor to an output pad. This is done in order to reduce the effects of mutual inductance between the various bondwires associated with the output of the RF amplifier device.

A semiconductor package according to an aspect of the present disclosure includes a package substrate and a plurality of semiconductor chips stacked on the package substrate. Each of the semiconductor chips includes a chip body, at least one first side power pad and at least one first side ground pad that are disposed on a first side portion on one surface of the chip body, and at least one second side power pad and at least one second side ground pad that are disposed on a second side portion opposite to the first side portion on one surface of the chip body. One of the second side power pads is disposed point-symmetrically to corresponding one of the first side power pads with respect to a reference point on the one surface, and one of the second side ground pads is disposed point-symmetrically to corresponding one of the first side ground pads with respect to a reference point on the one surface.

A wiring structure includes at least one upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer, at least one upper circuit layer in contact with the upper dielectric layer, and at least one bonding portion electrically connected to the upper circuit layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonding the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.

A semiconductor package includes a lower chip and an upper chip stacked on the lower chip. The lower chip includes lower chip pads arrayed in a plurality of lower columns on a top surface of the lower chip, wire bonding pads disposed on the top surface of the lower chip to be laterally spaced apart from the lower chip pads, and traces disposed on the top surface of the lower chip to electrically connect the lower chip pads to the wire bonding pads. The upper chip includes upper chip pads arrayed in a plurality of upper columns on a top surface of the upper chip and bumps disposed on the upper chip pads to contact the traces. The upper chip is stacked on the lower chip such that the top surface of the upper chip faces the top surface of the lower chip.

An optical coupling device includes a light receiving element provided with a first output terminal and a second output terminal, a light emitting element provided on the light receiving element, a first switching element, a first electrode plate, and a sealing member. The first switching element is provided side by side on the light receiving element. A first main terminal and a control terminal are provided on an upper surface of the first switching element. A second main terminal is provided on a lower surface of the first switching element. The first main terminal is connected to the first output terminal. The control terminal is connected to the second output terminal. An upper surface of the first electrode plate is connected to the second main terminal. The sealing member covers the light receiving element, the light emitting element, and the first switching element.

A semiconductor package may include: a chip stack including first to N.sup.th semiconductor chips stacked with an offset to one side such that edges thereof on the other side are exposed, and having first to N.sup.th chip pads disposed at the other-side edges, respectively; a bridge unit disposed adjacent to the other side of the chip stack and spaced apart from the chip stack; k.sup.th to N.sup.th wires extended in a vertical direction while one ends thereof are connected to the k.sup.th to N.sup.th chip pads among the first to Nth chip pads; first to (k−1).sup.th wires having one ends connected to the first to (k−1).sup.th chip pads among the first to N.sup.th chip pads; and an additional wire electrically coupled to the first to (k−1).sup.th wires, and extended in the vertical direction while one end thereof is connected to the bridge unit.