An isolation system and isolation device are disclosed. An illustrative isolation device is disclosed to include a transmitter circuit to generate a first current in accordance with a first signal, a first elongated conducting element to generate a magnetic field when the first current flows through the first elongated conducting element, a second elongated conducting element adjacent to the first elongated conducting element so as to receive the magnetic field. The second elongated conducting element is configured to generate an induced current when the magnetic field is received. The receiver circuit is configured to receive the induced current as an input, and configured to generate a reproduced first signal as an output of the receiver circuit.

Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

A semiconductor device with enhanced reliability. The semiconductor device has a wiring substrate which includes a first terminal electrically connected with a power supply potential supply section of a semiconductor chip, a first wiring coupling the power supply potential supply section with the first terminal, a second terminal electrically connected with a reference potential supply section of the semiconductor chip, and a second wiring coupling the reference potential supply section with the second terminal. The first terminal and second terminal are arranged closer to the periphery of the wiring substrate than the semiconductor chip. The second wiring is extended along the first wiring.

A semiconductor device includes a substrate, a semiconductor chip having a first surface bonded to the substrate and a second surface that is opposite to the first surface and includes a first electrode pad and a second electrode pad thereon, the first electrode pad being electrically connected to a circuit of the semiconductor chip that is operated during operation of the semiconductor device and the second electrode pad being electrically separated from the circuit, a first wire extending between the first electrode pad and a terminal of the substrate that is electrically connected with an external device during operation of the semiconductor device, a second wire extending between the second electrode pad and the substrate, and a resin layer formed over the second surface of the semiconductor chip and covering the first and second wires.

A semiconductor device with enhanced reliability. The semiconductor device has a wiring substrate which includes a first terminal electrically connected with a power supply potential supply section of a semiconductor chip, a first wiring coupling the power supply potential supply section with the first terminal, a second terminal electrically connected with a reference potential supply section of the semiconductor chip, and a second wiring coupling the reference potential supply section with the second terminal. The first terminal and second terminal are arranged closer to the periphery of the wiring substrate than the semiconductor chip. The second wiring is extended along the first wiring.

A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).

A semiconductor package is provided. The semiconductor package comprises a package substrate including first and second surfaces opposite to each other in a first direction, a plurality of substrate pads on the second surface, and first and second substrate edges respectively extending in a second direction intersecting the first direction and spaced apart from each other in a third direction intersecting the first and second directions, a first semiconductor chip on the package substrate, including third and fourth surfaces opposite to each other in the first direction, a plurality of chip pads and a plurality of chip dummy pad groups on the fourth surface, and first and second chip edges respectively extending in the second direction and spaced apart from each other in the third direction, and a plurality of first wires, each first wire of the plurality of first wires respectively connecting a respective substrate pad of the plurality of substrate pads with the plurality of chip pads, wherein the first chip edge is disposed to be closer to the first substrate edge than the second substrate edge, the plurality of substrate pads is disposed along the first substrate edge, the plurality of chip pads is disposed along the first chip edge, the first semiconductor chip includes third and fourth chip edges respectively extending in the third direction and spaced apart from each other in the second direction, a first corner formed at the intersection of the first chip edge and the third chip edge, a second corner formed at the intersection of first chip edge and the fourth chip edge, a third corner formed at the intersection of the second chip edge and the fourth chip edge, and a fourth corner formed at the intersection of the second chip edge and the third chip edge, and the plurality of chip dummy pad groups is respectively disposed on at least one of the first to fourth corners.