A packaged semiconductor device includes a lead frame and a semiconductor die. The semiconductor die has first and second opposing sides, and the first side of the die is mounted to the lead frame. A first set of bond wires and/or bump bonds are configured to electrically couple the die to the lead frame. A passive circuit element is on a substrate, and the substrate is mounted to the second side of the die. A second set of bond wires and/or bump bonds are configured to electrically couple the passive circuit element to the die. A molding material is configured to encapsulate the passive circuit element, the die, and at least a portion of the lead frame.

The present invention relates to semiconductor devices and integrated circuit packaging. In a specific embodiment, a semiconductor device comprising a double-sided fanout die package is provided. On one surface of a main circuit board for the semiconductor device, regular single-sided flip-chip dies and tall SMT components are coupled, along with one or more double-sided fanout dies, which are stacked with corresponding sub-sized circuit boards that are also coupled to the same surface, with a smaller height than the tallest surface mount device. A portion of the metal routing and grounding connections in the main circuit board for one or more double-sided fanout dies can be transferred to the sub-sized circuit boards, thereby reducing the area of the main circuit board without increasing the number of circuit board layers. There are other embodiments as well.

An electronic device has a fuse circuit including a semiconductor die and first and second bond wires, the semiconductor die having a bond pad and a fuse, the fuse having first and second portions, the bond pad coupled to the first portion of the fuse, and the second portion of the fuse coupled to a protected circuit, the first bond wire having a first end coupled to the bond pad and a second end coupled to a conductive terminal, and the second bond wire having a first end coupled to the second end of the first bond wire and a second end coupled to the conductive terminal.

A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.

Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.

Systems, methods, and devices related to techniques for repeating inter-die signals within a multi-die package of a memory device are disclosed. The multi-die package includes a memory stack including a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communicate with the first memory die via an inter-die connection. A technique involves incorporating the use of a multiplexer positioned in front of the transmitter of each die to facilitate repetition of inter-die signals within the memory stack as needed depending on various factors associated with the memory stack, such as, but not limited to, the type of signal, the intended recipient of the inter-die signals, and the stack height of the memory stack.

Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.