Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit board designed with a first side also designed to accept dual channel memory packages. Alternatively, dual channel memory packages may be mounted on a first side of a circuit board that is also designed to accept single channel packages on opposite sides.

A semiconductor package includes a package substrate, a logic chip on the package substrate, a memory stack structure on the package substrate and including first and second semiconductor chips stacked along a first direction, and a first bump between the package substrate and the memory stack structure. The logic chip and the memory stack are spaced apart along a second direction, crossing the first direction, on the package substrate. The first semiconductor chip includes a through via electrically connected to the second semiconductor chip, a chip signal pad connected to the through via, and a first redistribution layer electrically connected to the chip signal pad and having an edge signal pad in contact with the first bump. A distance between the logic chip and the edge signal pad along the second direction is less than that between the logic chip and the chip signal pad.

A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.

A method of manufacturing a semiconductor package includes disposing a buffer die on a support carrier; forming a plurality of memory dies, each of the plurality of memory dies having a body layer and an active layer on a surface of the body layer, wherein the body layer includes a light transmitting region; stacking the plurality of memory dies on the buffer die in a vertical direction to form a semiconductor device; measuring respective distances between the buffer die and the plurality of memory dies by irradiating light on the semiconductor device in the vertical direction; and forming a molding member encapsulating the semiconductor device.

A semiconductor package includes a connection substrate with a cavity, a first semiconductor chip and a second semiconductor chip on the connection substrate, a third semiconductor chip in the cavity of the connection substrate, the first semiconductor chip and the second semiconductor chip being on the third semiconductor chip and being connected to each other through the third semiconductor chip, and a molding layer that covers the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, wherein the third semiconductor chip includes first bumps that are exposed through the molding layer and are connected to the first semiconductor chip and the second semiconductor chip.

A semiconductor package may include a base wiring structure, a first bridge chip and a cache memory chip on the base wiring structure and spaced apart from each other in a horizontal direction, and logic semiconductor chips adjacent to each other on the first bridge chip and the cache memory chip. Logic semiconductor chips each may include a cache memory. The first bridge chip may overlap at least two of the logic semiconductor chips in a vertical direction and the first bridge chip may include first bridge wirings electrically connecting at least two of the logic semiconductor chips. The cache memory chip may overlap the cache memory of at least one of the logic semiconductor chips in the vertical direction and the cache memory chip may be electrically connected to the cache memory of at least one of the logic semiconductor chips.

Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.

A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

A wiring design method and a wiring structure for a package substrate in a flip chip, and a flip chip. The wiring design method includes: arranging bump pads in an array of rows and columns, wherein the bump pads are configured to bond with conductive bumps on a flip chip die, and the bump pads comprise signal pads and non-signal pads; providing the non-signal pad with a via hole; and using a layer of wiring to lead a subset of the signal pads out of an orthographic projection region of the flip chip die on the package substrate, wherein the subset of the signal pads is configured to carry all functional signals required by design specifications of the flip chip die for the array of the bump pads.