This specification relates to a packaging substrate and a manufacturing method for the packaging substrate. The packaging substrate according to this specification includes a core layer comprising a glass core having a first surface and a second surface facing each other, as well as a cavity portion penetrating through the glass core. An element module is arranged in the cavity portion, which includes a cavity element and a distribution layer formed on upper side of the cavity element. The cavity distribution layer includes a redistribution circuit layer and a cavity heat dissipation pattern, where the redistribution circuit layer includes i) a cavity bump layer; or ii) vias and circuit layers. The cavity heat dissipation pattern facilitates the movement of heat generated by the cavity element.

A semiconductor package includes a first substrate, a first semiconductor chip on an upper surface of the first substrate, a first bump between the first substrate and the first semiconductor chip, a first underfill layer that fills a center portion of a space between the first substrate and the first semiconductor chip, and a first molding member that covers an upper surface and side surfaces of the first semiconductor chip, and fills a periphery portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill layer in the space between the first substrate and the first semiconductor chip.

A semiconductor package includes a redistribution substrate and a semiconductor chip thereon. The redistribution substrate includes a ground under-bump pattern, signal under-bump patterns laterally spaced apart from the ground under-bump pattern, first signal line patterns disposed on the signal under-bump patterns and coupled to corresponding signal under-bump patterns, and a first ground pattern coupled to the ground under-bump pattern and laterally spaced apart from the first signal line pattern. Each of the signal and ground under-bump patterns includes a first part and a second part formed on the first part and that is wider than the first part. The second part of the ground under-bump pattern is wider than the second part of the signal under-bump pattern. The ground under-bump pattern vertically overlaps the first signal line patterns. The first ground pattern does not vertically overlap the signal under-bump patterns.

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure having a first surface and a second surface opposite to the first surface, a high-power die over the substrate structure, a lower-power die over the high-power die, a first interposer between the first surface of the substrate structure and the high-power die, and a second interposer between the high-power die and the lower-power die. The substrate structure includes a thermal enhancement portion located under the high-power die, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from other portions of the substrate structure. A substrate structure of the 3D integrated circuit package is also provided.

The invention provides a printed circuit board and a semiconductor package having the same, the printed circuit board includes traces disposed on respective upper and lower surfaces of the base layers and disposed on different vertical levels from a lowermost layer to an uppermost layer, and through vias connecting traces disposed on different vertical levels to each other and each extending in a vertical direction to pass through at least one of the base layers. The through vias include a first through via connecting the traces at the lowermost layer and the uppermost layer to each other, and a second through via connecting respective traces at adjacent intermediate layers between the lowermost layer and the uppermost layer to each other. The first through via passes through the inside of the second through via in the vertical direction, and the first through via is insulated from the second through via.

A stacked integrated circuit (IC) package includes: a package substrate; a first die stacked on the package substrate; second dies each stacked on the first die and spaced apart from each other on the first die; and a stiffener stacked on the first die and arranged between the second dies.

A 2.5D package includes an interposer, semiconductor chips on the interposer, an underfill member that is between the interposer and each of the semiconductor chips and between the interposer and an uppermost surface of one or more semiconductor chips of the semiconductor chips, and a mold on the interposer and a first sidewall of the one or more semiconductor chips, where the semiconductor chips define one or more recesses that are on the underfill member and at least partially expose a second sidewall of the one or more semiconductor chips, and where the second sidewall of the one or more semiconductor chips is opposite to the first sidewall of the one or more semiconductor chips.

Methods, systems, and devices for front-to-front bonding in a stacked memory system are described. The stacked memory system may include a package substrate and a volatile memory die with a front side. The stacked memory system may also include a logic die with a front side that is bonded with the front side of the volatile memory die. The back side of the stacked memory system may be coupled with a conductive bump that in turn is coupled with the package substrate.

An electronic module includes a wiring board having a first main surface and a second main surface on a back side of the first main surface, and a first semiconductor element and a second semiconductor element that are mounted on the wiring board. The first semiconductor element includes a first signal terminal and a second signal terminal. The second semiconductor element includes a third signal terminal and a fourth signal terminal. The wiring board includes a first signal line including a first signal trace disposed in a first conductor layer, a second signal line including a second signal trace disposed in a second conductor layer that is closer to the second main surface than the first conductor layer is, a first ground trace disposed in the first conductor layer, and a second ground trace disposed in the second conductor layer.

The present invention discloses a stacking system, which includes a system-on-wafer stacked on a photonic base, the photonic base provides a light transmission path, and a power base, which is configured above, below or beside the photon base, wherein the power base includes a power grid, a heat dissipation is stacked on the front of the system-on-wafer.