A microelectronic device includes a memory array structure, an additional memory array structure over and attached to the memory array structure, and a control circuitry structure over and attached to the additional memory array structure. The memory array structure includes an array region having memory cells. The additional memory array structure includes an additional array region having additional memory cells. The additional array region horizontally overlaps the array region. The control circuitry structure includes a control circuitry region horizontally overlapping each of the array region and the additional array region, and having control logic devices. The control logic devices are coupled to the memory cells and the additional memory cells. Gates of transistors of the control logic devices are positioned vertically closer to the additional memory cells than are channels of the transistors. Related methods and memory devices are also described.

A microelectronic device includes a memory array structure, an additional memory array structure over and attached to the memory array structure, and a control circuitry structure over and attached to the additional memory array structure. The memory array structure includes an array region having memory cells. The additional memory array structure includes an additional array region having additional memory cells. The additional array region horizontally overlaps the array region. The control circuitry structure includes a control circuitry region horizontally overlapping each of the array region and the additional array region and having control logic devices. The control logic devices are coupled to the memory cells and the additional memory cells. Channels of transistors of the control logic devices are positioned vertically closer to the additional memory cells than are gates of the transistors. Related methods and memory devices are also described.

A semiconductor package includes a buffer die; a plurality of core dies sequentially stacked on the buffer die via conductive bumps; and a plurality of adhesive layers between the plurality of core dies, the plurality of adhesive layers filling spaces between the conductive bumps and interconnecting the plurality of core dies; wherein each of the core dies of the plurality of core dies includes a middle region and diagonal regions that extend from the middle region to four corner portions of a respective core die, and wherein the conductive bumps includes: a plurality of first bump structures in the middle region, each first bump structure having a circular shape; and a plurality of second bump structures in each of the diagonal regions, each second bump structure having an elliptical shape.

A semiconductor package includes a lower redistribution wiring layer, a bridge chip provided on the lower redistribution wiring layer and having a bump structure, a sealing member covering the bridge chip on the lower redistribution wiring layer, a plurality of vertical conductive structures around the bridge chip and penetrating the sealing member, an upper redistribution wiring layer disposed on the sealing member, a first semiconductor device mounted on the upper redistribution wiring layer, and a second semiconductor device mounted on the upper redistribution wiring layer and spaced apart from the first semiconductor device, the second semiconductor device being electrically connected to the first semiconductor device by the bridge chip.

A die includes a first set of physical layer (PHY) blocks arranged in a first column, wherein the first column extends along a side of the die. The die also includes a second set of PHY blocks arranged in a second column adjacent to the first column. The first set of PHY blocks include a first PHY block, the second set of PHY blocks include a second PHY block, and the first PHY block and the second PHY block share one or more clock resources.

A package structure includes a first circuit substrate, a control circuit chip, a memory chip, a second circuit substrate, a plurality of conductive elements, a molding compound, and a plurality of solder balls. The control circuit chip and the memory chip are respective disposed on a first side and a second side of the first circuit substrate and electrically connected to the first circuit substrate. The memory chip, the conductive elements, and the molding compound are located between the second side of the first circuit substrate and a third side of the second circuit substrate. The conductive elements are electrically connected to the first circuit substrate and the second circuit substrate, and the molding compound covers the memory chip and the conductive elements. The solder balls are disposed on a fourth side of the second circuit substrate and electrically connected to the second circuit substrate.

Disclosed herein are methods, systems and devices including a substrate having a first attachment location and a second attachment location, a first photonic integrated circuit positioned within the first attachment location, a first connecting element positioned within the second attachment location, and a first multi-device package positioned on the substrate at least partially over the first attachment location and the second attachment location. In some embodiments, a second multi-device package may be positioned on the substrate at least partially over the second attachment location and electrically connected to the first multi-device package by the first connecting element.

A package substrate according to an embodiment may include a substrate that includes a core layer that includes a first region and a second region, a surface of the second region being recessed from a surface of the first region, and a first redistribution layer on the first region, the first redistribution layer including a first organic dielectric and a plurality of first circuit wiring lines inside the first organic dielectric, and a bridge die that is disposed on the second region and includes a connection layer that includes a glass bridge base and a plurality of wiring lines inside the glass bridge base, and a second redistribution layer on the connection layer, the second redistribution layer including an inorganic dielectric and a plurality of second circuit wiring lines inside the inorganic dielectric.

A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.

An underfill film may include a first film layer having a first dielectric constant, and a second film layer on the first film layer and having a second dielectric constant, where the second dielectric constant is higher than the first dielectric constant.