An output feedback control circuit includes, as a means for generating an error signal ERR between a feedback voltage FB commensurate with an output voltage and a reference voltage REF (means for substituting for a single error amplifier 140), a first signal processor (for example, an amplifier 140a) that forms a first path, and a second signal processor (for example, an amplifier 140b) that forms a second path. The amplifier 140a is more accurate than the amplifier 140b, and the amplifier 140b is faster than the amplifier 140a. To the output terminal of the amplifier 140a, preferably, a capacitor Cc other than a parasitic element is connected. To the output terminal of the amplifier 140b, preferably, no capacitor other than a parasitic element is connected, and a resistor Rc is connected. Preferably, the amplifier 140a has a transconductance gm1, and the amplifier 140b has a transconductance gm2 (≠gm1).

A semiconductor device includes: an operational amplifier; an external terminal configured to be attached to an external capacitor; and a resistor configured to be connected between a node, to which an output terminal and an inverting input terminal of the operational amplifier are connected in common, and the external terminal.

This present invention is an invented synchronous clock generator for the multiphase DC-DC converter system, comprising a front-end buffer circuit, a ramp signal generator circuit, a configurable equally divided reference voltage generator circuit, a set of comparators, a 10-ns pulse generator, multiple 30-ns pulse generators, and a pulse combination circuit. The synchronous clock generator can produce a clock pulse signal SYNC at N (total phase number) times the single-phase switching frequency. Within one synchronous loop period, a 10-ns pulse is first generated and followed by N-1 30-ns pulses. The master power stage chip detects the 10-ns pulse, and all the slave power stages detect and count the 30-ns pulses to determine when to set their output signal PWM. Thus, the invention can produce the new SYNC signal immediately with balanced phase shift while allowing the changing of the total phase number N by the total phase number register.

A switching regulator clamping the power or ground of the power switch driver is introduced. In a buck regulator, the power switch is coupled between the input terminal of the buck regulator and the first terminal of an inductor. The second terminal of the inductor is coupled to the output terminal of the buck regulator. There is a driver power clamp configured to clamp the ground terminal of the driver of the power switch. In a boost regulator, an inductor is provided which has a first terminal coupled to an input terminal of the boost regulator and has a second terminal coupled to the negative supply terminal of the power supply through a power switch. The boost regulator has a driver power clamp that is configured to clamp the power terminal of the driver of the power switch.

A converter to convert an input voltage into a regulated output current for supplying a load includes a reverse current protection diode having an anode coupled to the input voltage and a cathode, an energy storage element coupled to the cathode of the reverse current protection diode, a high side transistor coupled to the energy storage element and responsive to a high side control signal, and a low side transistor coupled to the energy storage element and responsive to a low side control signal. A controller is configured to generate the high side control signal and the low side control signal such that the low side transistor is enabled and the high side transistor is disabled during a pre-regulation interval.

System, device and method for exporting power are provided including at least one AC optimizer with plurality of DC inputs each connecting with respective one of plurality of DC sources, and independent maximum power point tracking (MPPT) performed for each respective DC source to extract power from each DC source for output and coupling to AC grid. When multiple AC optimizers are employed, with each AC optimizer having multiple DC inputs, each DC input can be connected to PV module with independent MPPT function. Since, each AC optimizer can serve multiple PV modules, significant cost saving and efficiencies can be achieved. Optionally, on PV sub-module level, each of the multiple DC inputs can be used as an independent MPPT channel for a PV sub-module cell string.

A power supply includes a reference voltage generator, a power supply phase, and an adjustor. During operation, the reference voltage generator produces a reference voltage. The power supply phase produces an output voltage to power a load as a function of an output voltage feedback signal derived from the output voltage and the reference voltage. The adjustor adjusts a magnitude of the reference voltage to maintain regulation of the output voltage with respect to a desired voltage setpoint.

A power semiconductor module including at least first and second power semiconductor elements, includes a first terminal, a first gate terminal, a second terminal, a second gate terminal, a third terminal and a common terminal. The first terminal connected to a first electrode of the first power semiconductor element. The first gate terminal connected to a gate of the first power semiconductor element. The second terminal connected to a first electrode of the second power semiconductor element. The second gate terminal connected to a gate of the second power semiconductor element. The third terminal connected to a second electrode of the first power semiconductor element and a second electrode of the second power semiconductor element. The common terminal that is connected to the first gate terminal through a first resistor and is connected to the second gate terminal through a second resistor.

A power converter with a negative current detection mechanism is provided. A negative current detecting circuit includes a first operational amplifier, a first transistor and a second transistor. A non-inverting input terminal of the first operational amplifier is connected to a second terminal of a sense resistor. An inverting input terminal of the first operational amplifier is connected to a first terminal of a first capacitor. Control terminals of the first and second transistors are connected to an output terminal of the first operational amplifier. A first terminal of the first transistor is connected to the second terminal of the sense resistor. A second terminal of the first transistor is grounded. A first terminal of the second transistor is connected to the inverting input terminal of the first operational amplifier and the first terminal of the first transistor. A second terminal of the second transistor is grounded.

In an embodiment, a wireless power transmitter includes: a master transmitter resonant tank configured to wirelessly transmit power to a receiver resonant tank; a master transmitter driver configured to drive the master transmitter resonant tank; a slave transmitter resonant tank; a slave transmitter driver configured to drive the slave transmitter resonant tank; and a controller configured to adjust an impedance seen by the master transmitter resonant tank by controlling the slave transmitter driver, where controlling the slave transmitter driver includes adjusting a phase angle between a slave transmitter current flowing through the slave transmitter resonant tank and a master transmitter current flowing through the master transmitter resonant tank or adjusting a slave supply voltage of the slave transmitter driver.