A switching power supply circuit can include: a transformer having a primary winding and a secondary winding; a resonant capacitor and a resonant inductor coupled in series with the primary winding to form a series structure; a power switch module receiving an input voltage and connecting two terminals of the series structure to form a resonance circuit; an output rectification module coupled to the secondary winding and generating an output voltage; an operating mode control module receiving the input voltage and the output voltage, to control the output rectification module such that the switching power supply circuit is operated in the LLC mode or the AHB mode based on a ratio of the input voltage and the output voltage relative to a predetermined value.

A control circuit for controlling a switching converter having a low quiescent current. The control circuit has an error amplifying circuit, an on time generator, a first comparing circuit and a second comparing circuit. When the switching converter operates in a light load operation mode, the error amplifying circuit and the on time generator are deactivated. Meanwhile, the first comparing circuit compares a current sensing signal indicative of inductor current with a current reference signal to provide an off time control signal during an on state of a low side switch to determine an on moment of a high side switch. The second comparing circuit compares the voltage feedback signal with a voltage reference signal to provide an on time control signal to determine an off moment of the high side switch.

A start-up routine for a Switched-Mode Power Supply (SMPS) gradually increases the duty cycle while reducing an initial dead time to a final optimal dead time for normal operation. Reliability is improved by the larger initial dead time that reduces ringing in switching transistors during low-voltage conditions early in the start-up sequence. Efficiency is improved by reducing the optimal dead time as voltages approach operating levels. The initial dead time is pre-calculated as a function of the input voltage and initial duty cycle. Optimal dead times are pre-calculated as a function of output voltage and output current. The optimal dead time is adjusted for each iteration of a second loop that also increases duty cycle until the target operating output voltage is reached. Pre-calculated dead times are based on the time required to fully charge and discharge parasitic drain-to-source capacitances in the switching transistors in the SMPS circuit.

A Battery Management System (BMS) inspects a battery pack using AC impedance. A controller on the BMS drives a Pulse-Width Modulation (PWM) output signal to an on-board excitation regulator such as a synchronous buck converter that modulates a limited energy unit such as a capacitor with a swept frequency of a PWM input signal. The capacitor modulations are applied to a terminal of the battery pack as an AC excitation signal. Synchronous sampling of the battery pack provides responses to the AC excitation signal. An AC excitation signal current and a battery response voltage are processed and Fourier-transformed to generate a Nyquist plot of the excitation-response data. Curve shifts can indicate worn battery cells. The capacitor generating the AC excitation signal draws little energy from the battery pack so AC impedance inspection can occur during all modes: charging, discharging, and idle modes without an external power supply.

Techniques for a sinking and sourcing power stage are provided. In an example, a power stage circuit can include a first power transistor configured to couple to a first input power rail, a second power transistor configured to couple to a second input power rail, an output node configured to couple to a load and to couple the first power transistor in series with the second power transistor between the first and second input power rails, and a controller configured to operate the first and second power transistors in a first mode to source current to the load and to operate the first and second power transistors in a second mode to sink current from the load.

In a power conversion apparatus including first to fourth semiconductor switching elements connected in series across both terminals of a high voltage-side capacitor, the third and fourth semiconductor switching elements are connected across both terminals of a low voltage-side capacitor via a reactor, and both terminals of the second and third semiconductor switching elements are connected across a charging-discharging capacitor. This charging-discharging capacitor includes a plurality of capacitor elements connected in parallel via a first wiring and a second wiring. Inductance components or capacitance components of the plurality of capacitor elements when viewed from an outflow-inflow portion of the first wiring and an outflow-inflow portion of the second wiring are different from each other such that the charging-discharging capacitor does not have a parallel resonance point in a driving frequency band but has a parallel resonance point in a noise frequency band.

A system is disclosed which allows for a multiphase Buck switching converter, where some phases operate in peak-mode current control, and some phases operate in valley-mode current control, simultaneously with the peak-mode phases. The peak-mode phases of the switching converter operate at lower frequency, and with a higher value inductor than the valley mode phases. The peak-mode phases support discontinuous control mode (DCM) operation and continuous control mode (CCM) operation, and the valley-mode phases only support CCM operation. The peak-mode phases of the switching converter are always enabled, and the valley-mode phases are only enabled at high currents. The peak-mode and valley-mode currents are matched with a peak current servo, for better efficiency.

Disclosed is an electronic circuit. The electronic circuit includes a first transistor device, a second transistor device, and a third transistor device, each having a control node and a load path. The electronic circuit further includes a drive circuit. The load paths of the first and second transistor devices are connected in parallel, the load path of the third transistor device is connected in series with the load paths of the first and second transistor devices, and the first transistor device and the second transistor device are integrated in a common semiconductor body. The drive circuit is configured, based on a control signal, to successively switch on the first transistor device and the second transistor device, so that the second transistor device is switched on when the first transistor device is in an on-state.

A switching converter comprising a regulation circuit adapted to regulate an output value of the converter based on a ramp signal is provided. A feedback circuit adapted to control at least one of a delay and a slope of the ramp signal based on a parameter of the ramp signal is also provided. A method of regulating an output value of a switching converter is also presented.

A controller for a voltage converter, such as a buck converter, includes: a switching regulator circuit having high side and low side switches; comparators configured to compare a voltage of an output circuit to reference voltages; and a control circuit coupled to the current comparators, configured to receive outputs from the comparators, and configured to generate a control signal for alternatingly switching the high side and low side switches off and on, such that the low side switch is off when the high side switch is on, and the high side switch is off when the low side switch is on, and wherein the control circuit includes a latching circuit configured to latch a signal corresponding to at least one of the outputs from the comparators. A method of operating a buck converter in connection with a fixed high-frequency automotive radar system, with reliable over-current detection, is also disclosed.