A topology for double-ended dual magnetic DC-DC SPC (“Voltage Doubler”) for all else being equal provides twice the output voltage as the conventional topology. The Voltage Doubler differs in that the secondary configuration is stacked in series as compared to the conventional topology in which the secondary configuration of the dual magnetics are in parallel. The output current is AC coupled rather than DC coupled to the load thereby doubling the output voltage. Because of the AC coupling, the Voltage Doubler is configured to automatically maintain balance of the secondary capacitors. During reset of the magnetics, the primary windings are shorted and both synchronous rectifier switches are closed. Due to transformer action, the output capacitors are connected to the output such that charge equalization forces the voltage on each capacitor to be equal.

An operation power source for an operation power source supplying power to a synchronous rectifier controller is charged according to the invention. The synchronous rectifier controller controls a synchronous rectifier in response to a channel signal of the synchronous rectifier, generating SR ON times and SR OFF times. It is determined whether the channel signal resonates in a first SR OFF time, to provide an oscillation record accordingly. In a second SR OFF time after the first SR OFF time, in response to the oscillation record, a portion of resonance energy that causes the channel signal resonating is directed to charge the operation power source.

A power converter is provided. The power converter includes an input side having a first input winding and a second input winding coupled in electrical series to the first input winding. The power converter also includes an output side having a first output winding and a second output winding coupled in electrical parallel to the first output winding.

An ideal diode circuit is described which uses an NMOS transistor as a low-loss ideal diode. The control circuit for the transistor is referenced to the anode voltage and not to ground, so the control circuitry may be low voltage circuitry, even if the input voltage is very high, referenced to earth ground. A capacitor is clamped to about 10-20 V, referenced to the anode voltage. The clamped voltage powers a differential amplifier for the detecting if the anode voltage is greater than the cathode voltage. The capacitor is charged to the clamped voltage during normal operation of the ideal diode by controlling the conductivity of a second transistor coupled between the cathode and the capacitor, enabling the circuit to be used with a wide range of frequencies and voltages. All voltages applied to the differential amplifier are equal to or less than the clamped voltage.

An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.

A power supply has a transformer, a rectifier switch, a secondary-side controller and two diodes. The transformer includes a primary winding, a secondary winding, and a detection winding, inductively coupling to one another. The rectifier switch is connected in series with the secondary winding between two output power lines. The secondary-side controller is electrically coupled to two ends of the detection winding, for controlling the rectifier switch in response to two terminal signals at the two ends respectively. The two diodes are back-to-back electrically connected in series between the two ends, and a joint connecting the two diodes is electrically connected to one of the two output power lines.

A secondary-side-controller for a QR flyback converter and method for operating the same are provided. Generally, the secondary-side-controller includes a driver configured to control a power-switch (PS) on a primary side of converter to turn on the PS when a sinusoidal input voltage to the converter is at one of a plurality of valleys, an analog-to-digital-converter (ADC) to read the input voltage, output voltage, and load current, and generate digital signals based thereon. A valley-controller coupled to the driver, ADC, a look-up-table and a pulse width modulator (PWM) receives the signals from the ADC and using the look-up-table determines at which valley of the plurality of valleys to couple a PWM signal from the PWM to the driver. The valley-controller is operable for each switching cycle of the PS to increment, decrement or leave unchanged the valley at which the PWM signal is coupled from the PWM to the driver.

The present invention discloses a method of standby power supply including steps of: detecting a loading level; determining the loading level; entering a select mode; selecting a standby mode; entering a no-load mode, or a sleep mode, or a power-down mode; during the no-load mode, generating a no-load sustaining power, and returning back to detect the loading level when a preset condition is met; during the sleep mode, generating a sleep sustaining power, and returning back to detect the loading level when the preset condition is met; during the power-down mode, ceasing the power and entering a power-down recovery mode; and during the power-down recovery mode, returning back to detect the loading level when the preset condition is met. Therefore, the present invention implements power conversion for normal power supply, and particularly effectively controls the amount of power in the standby state, thereby greatly reducing power consumption and improving power saving.

Disclosed is a three-phase interleaved resonant converter, which includes a three-phase inversion circuit connected to an input voltage and including a first output node, a second output node, and a third output node, a three-phase transformer including three transformers, a three-phase resonant circuit including three resonant capacitors and three resonant inductors, and a three-phase rectifier filter circuit. One ends of the three resonant inductors are respectively connected to the first output node, the second output node and the third output node, and the other ends of the three resonant inductors are respectively connected to a triangular configuration formed by an alternate connection of the three resonant capacitors with primary windings of the three transformers. The three-phase rectifier filter circuit is connected with secondary windings of the three transformers to rectify and filter secondary currents output by the secondary windings of the three transformers respectively, and generate an output voltage accordingly.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.