An AC-DC power converter includes a bridge circuit that has a first phase leg with first and second power switches connected to each other in series, a second phase leg with third and fourth power switches connected to each other in series. The first phase leg and the second phase leg are connected to the each other via a bridging connection to form the bridge circuit. The converter also includes means for providing power to said bridge circuit, and means for measuring an output voltage of said bridge circuit.

A system and method is disclosed, to generate an AC signal having a positive and negative half-cycles, each comprising a plurality of PWM pulses each with an individually designated pulse width, the system comprising: a first clock circuit; a second, faster, clock circuit; clock ratio measurement circuitry configured to output a first measurement being a ratio of frequencies; a propagation delay circuit configured to measure a number of propagation elements through which a bit transition propagates within a second clock signal period; pulse data calculation element configured to determine pulse shaping data; and for each of the half-cycles, a respective pulse synthesis circuit configured to synthesise the respective plurality of PWM pulses, each pulse having a respective start defined by the first clock signal, and a pulse width defined by the pulse shaping data and synthesised from the second clock and an output pulse from the propagation delay circuit.

A state estimation system for a power conversion semiconductor apparatus in an embodiment includes an analysis processing unit and an estimation processing unit. The analysis processing unit projects points indicating a combination of a voltage detection value in first time history data of a voltage between the pair of main terminals detected when the pair of main terminals are forward-biased and when the pair of main terminals are reverse-biased and a current detection value in second time history data of detection values of both a forward current and a reverse current between the pair of main terminals onto a coordinate plane including a voltage axis and a current axis on the basis of the first time history data and the second time history data in the power conversion semiconductor apparatus including the pair of main terminals and derives a distribution of the projected points on the coordinate plane. An estimation processing unit estimates a state of the power conversion semiconductor apparatus on the basis of a distribution of the projected points.

A stimulation circuit generates magnetic stimulation for application to a body organ using a coil arrangement. A DC supply is provided and supplied to a DC/AC inverter that comprises abridge inverter stage comprising plural switch modules connected in a bridge arrangement between input terminals and output terminals for supplying the stimulation signal. A driver circuit supplies pulse width modulation control signals to the switch modules that are selected to control the DC/AC inverter to generate the stimulation signal with pulse width modulation of voltage, thereby providing for a high degree of control of the form of the stimulation.

The present invention has steps of determining a minimum number of levels (L_duty) required to output a target modulation ratio (d_ref) (S2), determining the total number (N_volt) of voltage orders to be controlled among a voltage fundamental wave and harmonics of power converter (S3), comparing the minimum number of levels (L_duty) and the total number (N_volt) of voltage orders to be controlled and fixing a larger one as the number of switching times N in a quarter cycle for the target modulation ratio (S4-S6); when (N_volt) is fixed, determining shape of an output voltage (S7), and based on the target modulation ratio and the number of switching times N in the quarter cycle, determining switching phases for N times, and deriving the pulse pattern for one cycle by which each output voltage level according to the target modulation ratio, the output voltage shape and the phase is determined (S8, S9).

Apparatus and methods of providing digital varying output, such as sinusoidal, pulse width modulation, SPWM, control for an inverter comprising at least a first switch and a second switch are disclosed. The method comprising: generating a first binary control signal at a system modulation frequency; generating a second binary control signal at an M-times higher carrier frequency; wherein generating the second binary control signal comprises: providing a periodic counter having a K-times higher reset frequency; calculating M switch-off moments; determining for each, a corresponding switch-off counter value and a corresponding counter sequence value; storing each switch-off counter value in a respective memory location corresponding to the respective counter sequence and dummy values in the remaining memory locations; and sequentially and periodically transferring the contents of the memory locations to at least one PWM value register.

A common-mode voltage injection control method and apparatus for an inverter. For the method and apparatus, a common-mode voltage for a DPWM mode is calculated based on three-phase port voltages and an output power command; a common-mode voltage for an MPC modulation mode is calculated based on the direct current bus voltage, the three-phase port voltages, and the output power command; a modulation proportion is determined based on a maximum phase voltage peak value of the three-phase port voltages, the direct current bus voltage, and a power factor of the output power command; and a common-mode injection voltage is generated based on the common-mode voltage for the DPWM mode, the modulation proportion, and the common-mode voltage for the MPC modulation mode.

Electric machine drive systems, and related electric machine embodiments, include technologies for providing redundancy of shaft information of one or more electric machines between converter controllers of the corresponding system. The converter controllers are configured to control operation of power converters, which control one or more electric machines. The disclosed technologies include establishing one or more communication buses between the converter controllers to share the shaft information, which may be based on analog signals from a single, common resolver and/or from different, redundant resolvers depending on the embodiment. For example, in some embodiments, converter controllers communicatively connected to the same resolver may include separate resolver-to-digital converters (RDCs) to provide redundancy of the RDCs.

A three-level power converter includes a direct current power supply unit including a filter capacitor connected between a high potential line and an intermediate potential line and a filter capacitor connected between the intermediate potential line and a low potential line, and a power conversion circuit that converts a three-level direct current voltage output from the high potential line, the intermediate potential line, and the low potential line into a three-phase alternating current voltage. A controller generates an imbalance signal representing an imbalance between a first capacitor voltage and a second capacitor voltage on the basis of values detected by voltage sensors, and generates a modulation signal for causing the power conversion circuit to perform a two-phase modulation operation on the basis of a superimposed signal obtained by superimposing the imbalance signal on a reference signal of the three-phase alternating current voltage.

Electrical apparatus (20) includes an inverter (24) having input terminals for receiving DC input power and output terminals for coupling to an AC power grid. A pulse-width modulation (PWM) generator and drivers (26) drive the switches so as to control respective amplitudes, frequencies, and phases of the output current waveforms of the inverter. Control circuitry (28) receives measurements of respective time-varying voltages and currents on the input and output terminals, computes a model (40) that includes three virtual currents flowing in a synchronous machine that is emulated by the apparatus, wherein the three virtual currents are associated respectively with the three output current waveforms, and controls the PWM generator and drivers responsively to the three virtual currents so as to synchronize the amplitudes, frequencies, and phases of the three output current waveforms of the inverter with the three phases of the AC power grid.